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a4bcd67c72
There's already an SoC-specific conditional in cpu.h to determine the PLLP rate. Define the CSITE clock rate inside the same conditional, so that we can remove a conditional from clock_enable_coresight(). This means one less place to update the code for new SoCs. Signed-off-by: Stephen Warren <swarren@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> |
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.. | ||
tegra-common | ||
tegra20 | ||
tegra30 | ||
tegra114 | ||
config.mk | ||
cpu.c | ||
interrupts.c | ||
Makefile | ||
start.S |