mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-24 00:12:13 +00:00
5474fb894c
The freeze controller is required for FPGA partial reconfig. This node is disable on default. Enable this node via u-boot fdt command when needed. Signed-off-by: Yau Wai Gan <yau.wai.gan@intel.com> Signed-off-by: Dinesh Maniyam <dinesh.maniyam@intel.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
49 lines
749 B
Text
Executable file
49 lines
749 B
Text
Executable file
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* U-Boot additions
|
|
*
|
|
* Copyright (C) 2019-2022 Intel Corporation <www.intel.com>
|
|
*/
|
|
|
|
#include "socfpga_stratix10-u-boot.dtsi"
|
|
|
|
/{
|
|
aliases {
|
|
spi0 = &qspi;
|
|
freeze_br0 = &freeze_controller;
|
|
};
|
|
|
|
soc {
|
|
freeze_controller: freeze_controller@f9000450 {
|
|
compatible = "altr,freeze-bridge-controller";
|
|
reg = <0xf9000450 0x00000010>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
&clkmgr {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&flash0 {
|
|
compatible = "jedec,spi-nor";
|
|
spi-max-frequency = <100000000>;
|
|
spi-tx-bus-width = <4>;
|
|
spi-rx-bus-width = <4>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&sysmgr {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&watchdog0 {
|
|
status = "okay";
|
|
u-boot,dm-pre-reloc;
|
|
};
|