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https://github.com/AsahiLinux/u-boot
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35e29e89a3
Enabling and disabling PCIe ports is done via address space of system controller. All 32-bit Armada SoCs use low 4 bits in SoC Control 1 Register for enabling and disabling some or more PCIe ports. Correct mapping needs to be set in particular DTS files. DT API for mvebu-reset is prepared for implementing resets also for other HW blocks, but currently only PCIe is implemented via index 0. Currently this driver is not used as PCIe ports are automatically enabled by SerDes code executed by U-Boot SPL. But this will change in followup patches. Signed-off-by: Pali Rohár <pali@kernel.org>
665 lines
16 KiB
Text
665 lines
16 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Marvell Armada 38x family of SoCs.
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*
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* Copyright (C) 2014 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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/ {
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model = "Marvell Armada 38x family SoC";
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compatible = "marvell,armada380";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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serial0 = &uart0;
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serial1 = &uart1;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts-extended = <&mpic 3>;
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};
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soc {
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compatible = "marvell,armada380-mbus", "simple-bus";
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u-boot,dm-pre-reloc;
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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interrupt-parent = <&gic>;
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pcie-mem-aperture = <0xe0000000 0x8000000>;
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pcie-io-aperture = <0xe8000000 0x100000>;
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bootrom {
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
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};
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devbus_bootcs: devbus-bootcs {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus_cs0: devbus-cs0 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus_cs1: devbus-cs1 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus_cs2: devbus-cs2 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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devbus_cs3: devbus-cs3 {
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compatible = "marvell,mvebu-devbus";
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reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
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ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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internal-regs {
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compatible = "simple-bus";
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
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L2: cache-controller@8000 {
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compatible = "arm,pl310-cache";
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reg = <0x8000 0x1000>;
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cache-unified;
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cache-level = <2>;
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arm,double-linefill-incr = <0>;
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arm,double-linefill-wrap = <0>;
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arm,double-linefill = <0>;
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prefetch-data = <1>;
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};
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scu@c000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xc000 0x58>;
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};
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timer@c200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0xc200 0x20>;
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interrupts = <GIC_PPI 11 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
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clocks = <&coreclk 2>;
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};
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timer@c600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xc600 0x20>;
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interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
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clocks = <&coreclk 2>;
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};
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gic: interrupt-controller@d000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#size-cells = <0>;
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interrupt-controller;
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reg = <0xd000 0x1000>,
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<0xc100 0x100>;
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};
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i2c0: i2c@11000 {
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compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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i2c1: i2c@11100 {
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compatible = "marvell,mv78230-a0-i2c", "marvell,mv64xxx-i2c";
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reg = <0x11100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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uart0: serial@12000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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uart1: serial@12100 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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pinctrl: pinctrl@18000 {
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reg = <0x18000 0x20>;
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ge0_rgmii_pins: ge-rgmii-pins-0 {
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marvell,pins = "mpp6", "mpp7", "mpp8",
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"mpp9", "mpp10", "mpp11",
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"mpp12", "mpp13", "mpp14",
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"mpp15", "mpp16", "mpp17";
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marvell,function = "ge0";
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};
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ge1_rgmii_pins: ge-rgmii-pins-1 {
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marvell,pins = "mpp21", "mpp27", "mpp28",
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"mpp29", "mpp30", "mpp31",
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"mpp32", "mpp37", "mpp38",
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"mpp39", "mpp40", "mpp41";
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marvell,function = "ge1";
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};
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i2c0_pins: i2c-pins-0 {
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marvell,pins = "mpp2", "mpp3";
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marvell,function = "i2c0";
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};
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mdio_pins: mdio-pins {
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marvell,pins = "mpp4", "mpp5";
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marvell,function = "ge";
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};
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ref_clk0_pins: ref-clk-pins-0 {
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marvell,pins = "mpp45";
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marvell,function = "ref";
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};
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ref_clk1_pins: ref-clk-pins-1 {
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marvell,pins = "mpp46";
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marvell,function = "ref";
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};
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spi0_pins: spi-pins-0 {
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marvell,pins = "mpp22", "mpp23", "mpp24",
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"mpp25";
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marvell,function = "spi0";
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};
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spi1_pins: spi-pins-1 {
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marvell,pins = "mpp56", "mpp57", "mpp58",
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"mpp59";
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marvell,function = "spi1";
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};
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nand_pins: nand-pins {
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marvell,pins = "mpp22", "mpp34", "mpp23",
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"mpp33", "mpp38", "mpp28",
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"mpp40", "mpp42", "mpp35",
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"mpp36", "mpp25", "mpp30",
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"mpp32";
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marvell,function = "dev";
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};
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nand_rb: nand-rb {
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marvell,pins = "mpp41";
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marvell,function = "nand";
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};
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uart0_pins: uart-pins-0 {
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marvell,pins = "mpp0", "mpp1";
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marvell,function = "ua0";
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};
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uart1_pins: uart-pins-1 {
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marvell,pins = "mpp19", "mpp20";
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marvell,function = "ua1";
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};
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sdhci_pins: sdhci-pins {
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marvell,pins = "mpp48", "mpp49", "mpp50",
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"mpp52", "mpp53", "mpp54",
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"mpp55", "mpp57", "mpp58",
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"mpp59";
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marvell,function = "sd0";
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};
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sata0_pins: sata-pins-0 {
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marvell,pins = "mpp20";
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marvell,function = "sata0";
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};
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sata1_pins: sata-pins-1 {
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marvell,pins = "mpp19";
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marvell,function = "sata1";
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};
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sata2_pins: sata-pins-2 {
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marvell,pins = "mpp47";
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marvell,function = "sata2";
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};
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sata3_pins: sata-pins-3 {
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marvell,pins = "mpp44";
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marvell,function = "sata3";
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};
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};
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gpio0: gpio@18100 {
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compatible = "marvell,armada-370-gpio",
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"marvell,orion-gpio";
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reg = <0x18100 0x40>, <0x181c0 0x08>;
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reg-names = "gpio", "pwm";
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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#pwm-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&coreclk 0>;
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};
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gpio1: gpio@18140 {
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compatible = "marvell,armada-370-gpio",
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"marvell,orion-gpio";
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reg = <0x18140 0x40>, <0x181c8 0x08>;
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reg-names = "gpio", "pwm";
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ngpios = <28>;
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gpio-controller;
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#gpio-cells = <2>;
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#pwm-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&coreclk 0>;
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};
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systemc: system-controller@18200 {
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compatible = "marvell,armada-380-system-controller",
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"marvell,armada-370-xp-system-controller";
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reg = <0x18200 0x100>;
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#reset-cells = <2>;
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};
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gateclk: clock-gating-control@18220 {
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compatible = "marvell,armada-380-gating-clock";
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reg = <0x18220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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coreclk: mvebu-sar@18600 {
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compatible = "marvell,armada-380-core-clock";
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reg = <0x18600 0x04>;
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#clock-cells = <1>;
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};
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mbusc: mbus-controller@20000 {
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compatible = "marvell,mbus-controller";
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reg = <0x20000 0x100>, <0x20180 0x20>,
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<0x20250 0x8>;
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};
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mpic: interrupt-controller@20a00 {
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compatible = "marvell,mpic";
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reg = <0x20a00 0x2d0>, <0x21070 0x58>;
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#interrupt-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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msi-controller;
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interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer: timer@20300 {
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compatible = "marvell,armada-380-timer",
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"marvell,armada-xp-timer";
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reg = <0x20300 0x30>, <0x21040 0x30>;
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interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<&mpic 5>,
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<&mpic 6>;
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clocks = <&coreclk 2>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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watchdog: watchdog@20300 {
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compatible = "marvell,armada-380-wdt";
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reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
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clocks = <&coreclk 2>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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cpurst: cpurst@20800 {
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compatible = "marvell,armada-370-cpu-reset";
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reg = <0x20800 0x10>;
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};
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mpcore-soc-ctrl@20d20 {
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compatible = "marvell,armada-380-mpcore-soc-ctrl";
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reg = <0x20d20 0x6c>;
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};
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coherencyfab: coherency-fabric@21010 {
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compatible = "marvell,armada-380-coherency-fabric";
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reg = <0x21010 0x1c>;
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};
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pmsu: pmsu@22000 {
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compatible = "marvell,armada-380-pmsu";
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reg = <0x22000 0x1000>;
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};
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/*
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* As a special exception to the "order by
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* register address" rule, the eth0 node is
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* placed here to ensure that it gets
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* registered as the first interface, since
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* the network subsystem doesn't allow naming
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* interfaces using DT aliases. Without this,
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* the ordering of interfaces is different
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* from the one used in U-Boot and the
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* labeling of interfaces on the boards, which
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* is very confusing for users.
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*/
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eth0: ethernet@70000 {
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compatible = "marvell,armada-370-neta";
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reg = <0x70000 0x4000>;
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interrupts-extended = <&mpic 8>;
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clocks = <&gateclk 4>;
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tx-csum-limit = <9800>;
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status = "disabled";
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};
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eth1: ethernet@30000 {
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compatible = "marvell,armada-370-neta";
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reg = <0x30000 0x4000>;
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interrupts-extended = <&mpic 10>;
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clocks = <&gateclk 3>;
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status = "disabled";
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};
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eth2: ethernet@34000 {
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compatible = "marvell,armada-370-neta";
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reg = <0x34000 0x4000>;
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interrupts-extended = <&mpic 12>;
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clocks = <&gateclk 2>;
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status = "disabled";
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};
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usb0: usb@58000 {
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compatible = "marvell,orion-ehci";
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reg = <0x58000 0x500>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gateclk 18>;
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status = "disabled";
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};
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xor0: xor@60800 {
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compatible = "marvell,armada-380-xor", "marvell,orion-xor";
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reg = <0x60800 0x100
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0x60a00 0x100>;
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clocks = <&gateclk 22>;
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status = "okay";
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xor00 {
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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xor1: xor@60900 {
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compatible = "marvell,armada-380-xor", "marvell,orion-xor";
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reg = <0x60900 0x100
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0x60b00 0x100>;
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clocks = <&gateclk 28>;
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status = "okay";
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xor10 {
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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dmacap,memcpy;
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dmacap,xor;
|
|
dmacap,memset;
|
|
};
|
|
};
|
|
|
|
mdio: mdio@72004 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "marvell,orion-mdio";
|
|
reg = <0x72004 0x4>;
|
|
clocks = <&gateclk 4>;
|
|
};
|
|
|
|
cesa: crypto@90000 {
|
|
compatible = "marvell,armada-38x-crypto";
|
|
reg = <0x90000 0x10000>;
|
|
reg-names = "regs";
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gateclk 23>, <&gateclk 21>,
|
|
<&gateclk 14>, <&gateclk 16>;
|
|
clock-names = "cesa0", "cesa1",
|
|
"cesaz0", "cesaz1";
|
|
marvell,crypto-srams = <&crypto_sram0>,
|
|
<&crypto_sram1>;
|
|
marvell,crypto-sram-size = <0x800>;
|
|
};
|
|
|
|
rtc: rtc@a3800 {
|
|
compatible = "marvell,armada-380-rtc";
|
|
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
|
|
reg-names = "rtc", "rtc-soc";
|
|
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
ahci0: sata@a8000 {
|
|
compatible = "marvell,armada-380-ahci";
|
|
reg = <0xa8000 0x2000>;
|
|
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gateclk 15>;
|
|
status = "disabled";
|
|
};
|
|
|
|
bm: bm@c8000 {
|
|
compatible = "marvell,armada-380-neta-bm";
|
|
reg = <0xc8000 0xac>;
|
|
clocks = <&gateclk 13>;
|
|
internal-mem = <&bm_bppi>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ahci1: sata@e0000 {
|
|
compatible = "marvell,armada-380-ahci";
|
|
reg = <0xe0000 0x2000>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gateclk 30>;
|
|
status = "disabled";
|
|
};
|
|
|
|
coredivclk: clock@e4250 {
|
|
compatible = "marvell,armada-380-corediv-clock";
|
|
reg = <0xe4250 0xc>;
|
|
#clock-cells = <1>;
|
|
clocks = <&mainpll>;
|
|
clock-output-names = "nand";
|
|
};
|
|
|
|
thermal: thermal@e8078 {
|
|
compatible = "marvell,armada380-thermal";
|
|
reg = <0xe4078 0x4>, <0xe4070 0x8>;
|
|
status = "okay";
|
|
};
|
|
|
|
nand_controller: nand-controller@d0000 {
|
|
compatible = "marvell,armada370-nand","marvell,mvebu-pxa3xx-nand";
|
|
reg = <0xd0000 0x54>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&coredivclk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci: sdhci@d8000 {
|
|
compatible = "marvell,armada-380-sdhci";
|
|
reg-names = "sdhci", "mbus", "conf-sdio3";
|
|
reg = <0xd8000 0x1000>,
|
|
<0xdc000 0x100>,
|
|
<0x18454 0x4>;
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gateclk 17>;
|
|
mrvl,clk-delay-cycles = <0x1F>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3_0: usb3@f0000 {
|
|
compatible = "marvell,armada-380-xhci";
|
|
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gateclk 9>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb3_1: usb3@f8000 {
|
|
compatible = "marvell,armada-380-xhci";
|
|
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&gateclk 10>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
crypto_sram0: sa-sram0 {
|
|
compatible = "mmio-sram";
|
|
reg = <MBUS_ID(0x09, 0x19) 0 0x800>;
|
|
clocks = <&gateclk 23>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 MBUS_ID(0x09, 0x19) 0 0x800>;
|
|
};
|
|
|
|
crypto_sram1: sa-sram1 {
|
|
compatible = "mmio-sram";
|
|
reg = <MBUS_ID(0x09, 0x15) 0 0x800>;
|
|
clocks = <&gateclk 21>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
|
|
};
|
|
|
|
bm_bppi: bm-bppi {
|
|
compatible = "mmio-sram";
|
|
reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
|
|
ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
clocks = <&gateclk 13>;
|
|
no-memory-wc;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi0: spi@10600 {
|
|
compatible = "marvell,armada-380-spi",
|
|
"marvell,orion-spi";
|
|
reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&coreclk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@10680 {
|
|
compatible = "marvell,armada-380-spi",
|
|
"marvell,orion-spi";
|
|
reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <1>;
|
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&coreclk 0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
/* 1 GHz fixed main PLL */
|
|
mainpll: mainpll {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <1000000000>;
|
|
};
|
|
|
|
/* 25 MHz reference crystal */
|
|
refclk: oscillator {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <25000000>;
|
|
};
|
|
};
|
|
};
|