mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
ee73135365
Synced from Linux commit 3650b228f83a ("Linux 5.10-rc1")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
107 lines
2 KiB
Text
107 lines
2 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Copyright (c) 2019 BayLibre, SAS
|
|
* Author: Neil Armstrong <narmstrong@baylibre.com>
|
|
* Copyright (c) 2019 Christian Hewitt <christianshewitt@gmail.com>
|
|
*/
|
|
|
|
/ {
|
|
model = "Khadas VIM3";
|
|
|
|
vddcpu_a: regulator-vddcpu-a {
|
|
/*
|
|
* MP8756GD Regulator.
|
|
*/
|
|
compatible = "pwm-regulator";
|
|
|
|
regulator-name = "VDDCPU_A";
|
|
regulator-min-microvolt = <690000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
|
|
vin-supply = <&dc_in>;
|
|
|
|
pwms = <&pwm_ab 0 1250 0>;
|
|
pwm-dutycycle-range = <100 0>;
|
|
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
|
|
vddcpu_b: regulator-vddcpu-b {
|
|
/*
|
|
* Silergy SY8030DEC Regulator.
|
|
*/
|
|
compatible = "pwm-regulator";
|
|
|
|
regulator-name = "VDDCPU_B";
|
|
regulator-min-microvolt = <690000>;
|
|
regulator-max-microvolt = <1050000>;
|
|
|
|
vin-supply = <&vsys_3v3>;
|
|
|
|
pwms = <&pwm_AO_cd 1 1250 0>;
|
|
pwm-dutycycle-range = <100 0>;
|
|
|
|
regulator-boot-on;
|
|
regulator-always-on;
|
|
};
|
|
};
|
|
|
|
&cpu0 {
|
|
cpu-supply = <&vddcpu_b>;
|
|
operating-points-v2 = <&cpu_opp_table_0>;
|
|
clocks = <&clkc CLKID_CPU_CLK>;
|
|
clock-latency = <50000>;
|
|
};
|
|
|
|
&cpu1 {
|
|
cpu-supply = <&vddcpu_b>;
|
|
operating-points-v2 = <&cpu_opp_table_0>;
|
|
clocks = <&clkc CLKID_CPU_CLK>;
|
|
clock-latency = <50000>;
|
|
};
|
|
|
|
&cpu100 {
|
|
cpu-supply = <&vddcpu_a>;
|
|
operating-points-v2 = <&cpub_opp_table_1>;
|
|
clocks = <&clkc CLKID_CPUB_CLK>;
|
|
clock-latency = <50000>;
|
|
};
|
|
|
|
&cpu101 {
|
|
cpu-supply = <&vddcpu_a>;
|
|
operating-points-v2 = <&cpub_opp_table_1>;
|
|
clocks = <&clkc CLKID_CPUB_CLK>;
|
|
clock-latency = <50000>;
|
|
};
|
|
|
|
&cpu102 {
|
|
cpu-supply = <&vddcpu_a>;
|
|
operating-points-v2 = <&cpub_opp_table_1>;
|
|
clocks = <&clkc CLKID_CPUB_CLK>;
|
|
clock-latency = <50000>;
|
|
};
|
|
|
|
&cpu103 {
|
|
cpu-supply = <&vddcpu_a>;
|
|
operating-points-v2 = <&cpub_opp_table_1>;
|
|
clocks = <&clkc CLKID_CPUB_CLK>;
|
|
clock-latency = <50000>;
|
|
};
|
|
|
|
&pwm_ab {
|
|
pinctrl-0 = <&pwm_a_e_pins>;
|
|
pinctrl-names = "default";
|
|
clocks = <&xtal>;
|
|
clock-names = "clkin0";
|
|
status = "okay";
|
|
};
|
|
|
|
&pwm_AO_cd {
|
|
pinctrl-0 = <&pwm_ao_d_e_pins>;
|
|
pinctrl-names = "default";
|
|
clocks = <&xtal>;
|
|
clock-names = "clkin1";
|
|
status = "okay";
|
|
};
|
|
|