mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-05 02:51:00 +00:00
1b2fd5bf4e
Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
65 lines
1.2 KiB
C
65 lines
1.2 KiB
C
/*
|
|
* (C) Copyright 2015 Google, Inc
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0
|
|
*/
|
|
|
|
#ifndef _ASM_ARCH_CLOCK_H
|
|
#define _ASM_ARCH_CLOCK_H
|
|
|
|
/* define pll mode */
|
|
#define RKCLK_PLL_MODE_SLOW 0
|
|
#define RKCLK_PLL_MODE_NORMAL 1
|
|
|
|
enum {
|
|
ROCKCHIP_SYSCON_NOC,
|
|
ROCKCHIP_SYSCON_GRF,
|
|
ROCKCHIP_SYSCON_SGRF,
|
|
ROCKCHIP_SYSCON_PMU,
|
|
};
|
|
|
|
/* Standard Rockchip clock numbers */
|
|
enum rk_clk_id {
|
|
CLK_OSC,
|
|
CLK_ARM,
|
|
CLK_DDR,
|
|
CLK_CODEC,
|
|
CLK_GENERAL,
|
|
CLK_NEW,
|
|
|
|
CLK_COUNT,
|
|
};
|
|
|
|
static inline int rk_pll_id(enum rk_clk_id clk_id)
|
|
{
|
|
return clk_id - 1;
|
|
}
|
|
|
|
/**
|
|
* clk_get_divisor() - Calculate the required clock divisior
|
|
*
|
|
* Given an input rate and a required output_rate, calculate the Rockchip
|
|
* divisor needed to achieve this.
|
|
*
|
|
* @input_rate: Input clock rate in Hz
|
|
* @output_rate: Output clock rate in Hz
|
|
* @return divisor register value to use
|
|
*/
|
|
static inline u32 clk_get_divisor(ulong input_rate, uint output_rate)
|
|
{
|
|
uint clk_div;
|
|
|
|
clk_div = input_rate / output_rate;
|
|
clk_div = (clk_div + 1) & 0xfffe;
|
|
|
|
return clk_div;
|
|
}
|
|
|
|
/**
|
|
* rockchip_get_cru() - get a pointer to the clock/reset unit registers
|
|
*
|
|
* @return pointer to registers, or -ve error on error
|
|
*/
|
|
void *rockchip_get_cru(void);
|
|
|
|
#endif
|