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50e54e8067
Add support for the RK3588 variant to the driver. Code imported almost 1:1 from mainline linux driver. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
279 lines
6.6 KiB
C
279 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Rockchip PCIE3.0 phy driver
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*
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* Copyright (C) 2021 Rockchip Electronics Co., Ltd.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <regmap.h>
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#include <reset-uclass.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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/* Register for RK3568 */
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#define GRF_PCIE30PHY_CON1 0x4
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#define GRF_PCIE30PHY_CON6 0x18
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#define GRF_PCIE30PHY_CON9 0x24
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#define GRF_PCIE30PHY_DA_OCM (BIT(15) | BIT(31))
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#define GRF_PCIE30PHY_STATUS0 0x80
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#define GRF_PCIE30PHY_WR_EN (0xf << 16)
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#define SRAM_INIT_DONE(reg) (reg & BIT(14))
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#define RK3568_BIFURCATION_LANE_0_1 BIT(0)
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/* Register for RK3588 */
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#define PHP_GRF_PCIESEL_CON 0x100
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#define RK3588_PCIE3PHY_GRF_CMN_CON0 0x0
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#define RK3588_PCIE3PHY_GRF_PHY0_STATUS1 0x904
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#define RK3588_PCIE3PHY_GRF_PHY1_STATUS1 0xa04
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#define RK3588_SRAM_INIT_DONE(reg) (reg & BIT(0))
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#define RK3588_BIFURCATION_LANE_0_1 BIT(0)
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#define RK3588_BIFURCATION_LANE_2_3 BIT(1)
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#define RK3588_LANE_AGGREGATION BIT(2)
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/**
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* struct rockchip_p3phy_priv - RK DW PCIe PHY state
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*
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* @mmio: The base address of PHY internal registers
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* @phy_grf: The regmap for controlling pipe signal
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* @p30phy: The reset signal for PHY
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* @clks: The clocks for PHY
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* @num_lanes: The number of lane to controller mappings
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* @lanes: The lane to controller mapping
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*/
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struct rockchip_p3phy_priv {
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void __iomem *mmio;
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struct regmap *phy_grf;
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struct regmap *pipe_grf;
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struct reset_ctl p30phy;
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struct clk_bulk clks;
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int num_lanes;
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u32 lanes[4];
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};
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struct rockchip_p3phy_ops {
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int (*phy_init)(struct phy *phy);
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};
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static int rockchip_p3phy_rk3568_init(struct phy *phy)
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{
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struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
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bool bifurcation = false;
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int ret;
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u32 reg;
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/* Deassert PCIe PMA output clamp mode */
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9, GRF_PCIE30PHY_DA_OCM);
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for (int i = 0; i < priv->num_lanes; i++) {
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if (priv->lanes[i] > 1)
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bifurcation = true;
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}
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/* Set bifurcation if needed, and it doesn't care RC/EP */
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if (bifurcation) {
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
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GRF_PCIE30PHY_WR_EN | RK3568_BIFURCATION_LANE_0_1);
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON1,
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GRF_PCIE30PHY_DA_OCM);
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} else {
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regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON6,
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GRF_PCIE30PHY_WR_EN & ~RK3568_BIFURCATION_LANE_0_1);
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}
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reset_deassert(&priv->p30phy);
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udelay(1);
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ret = regmap_read_poll_timeout(priv->phy_grf,
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GRF_PCIE30PHY_STATUS0,
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reg, SRAM_INIT_DONE(reg),
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0, 500);
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if (ret)
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dev_err(phy->dev, "lock failed 0x%x\n", reg);
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return ret;
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}
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static const struct rockchip_p3phy_ops rk3568_ops = {
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.phy_init = rockchip_p3phy_rk3568_init,
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};
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static int rockchip_p3phy_rk3588_init(struct phy *phy)
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{
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struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
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u32 reg = 0;
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u8 mode = 0;
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int ret;
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/* Deassert PCIe PMA output clamp mode */
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regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
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BIT(8) | BIT(24));
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/* Set bifurcation if needed */
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for (int i = 0; i < priv->num_lanes; i++) {
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if (!priv->lanes[i])
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mode |= (BIT(i) << 3);
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if (priv->lanes[i] > 1)
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mode |= (BIT(i) >> 1);
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}
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if (!mode) {
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reg = RK3588_LANE_AGGREGATION;
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} else {
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if (mode & (BIT(0) | BIT(1)))
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reg |= RK3588_BIFURCATION_LANE_0_1;
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if (mode & (BIT(2) | BIT(3)))
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reg |= RK3588_BIFURCATION_LANE_2_3;
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}
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regmap_write(priv->phy_grf, RK3588_PCIE3PHY_GRF_CMN_CON0,
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(0x7 << 16) | reg);
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/* Set pcie1ln_sel in PHP_GRF_PCIESEL_CON */
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reg = (mode & (BIT(6) | BIT(7))) >> 6;
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if (reg)
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regmap_write(priv->pipe_grf, PHP_GRF_PCIESEL_CON,
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(reg << 16) | reg);
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reset_deassert(&priv->p30phy);
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udelay(1);
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ret = regmap_read_poll_timeout(priv->phy_grf,
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RK3588_PCIE3PHY_GRF_PHY0_STATUS1,
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reg, RK3588_SRAM_INIT_DONE(reg),
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0, 500);
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ret |= regmap_read_poll_timeout(priv->phy_grf,
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RK3588_PCIE3PHY_GRF_PHY1_STATUS1,
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reg, RK3588_SRAM_INIT_DONE(reg),
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0, 500);
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if (ret)
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dev_err(phy->dev, "lock failed 0x%x\n", reg);
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return ret;
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}
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static const struct rockchip_p3phy_ops rk3588_ops = {
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.phy_init = rockchip_p3phy_rk3588_init,
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};
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static int rochchip_p3phy_init(struct phy *phy)
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{
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struct rockchip_p3phy_ops *ops =
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(struct rockchip_p3phy_ops *)dev_get_driver_data(phy->dev);
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struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
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int ret;
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ret = clk_enable_bulk(&priv->clks);
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if (ret)
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return ret;
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reset_assert(&priv->p30phy);
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udelay(1);
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ret = ops->phy_init(phy);
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if (ret)
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clk_disable_bulk(&priv->clks);
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return ret;
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}
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static int rochchip_p3phy_exit(struct phy *phy)
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{
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struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
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clk_disable_bulk(&priv->clks);
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reset_assert(&priv->p30phy);
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return 0;
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}
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static int rockchip_p3phy_probe(struct udevice *dev)
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{
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struct rockchip_p3phy_priv *priv = dev_get_priv(dev);
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int ret;
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priv->mmio = dev_read_addr_ptr(dev);
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if (!priv->mmio)
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return -EINVAL;
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priv->phy_grf = syscon_regmap_lookup_by_phandle(dev, "rockchip,phy-grf");
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if (IS_ERR(priv->phy_grf)) {
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dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
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return PTR_ERR(priv->phy_grf);
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}
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if (device_is_compatible(dev, "rockchip,rk3588-pcie3-phy")) {
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priv->pipe_grf =
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syscon_regmap_lookup_by_phandle(dev, "rockchip,pipe-grf");
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if (IS_ERR(priv->pipe_grf)) {
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dev_err(dev, "failed to find rockchip,pipe_grf regmap\n");
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return PTR_ERR(priv->pipe_grf);
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}
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}
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ret = dev_read_size(dev, "data-lanes");
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if (ret > 0) {
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priv->num_lanes = ret / sizeof(u32);
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if (priv->num_lanes < 2 ||
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priv->num_lanes > ARRAY_SIZE(priv->lanes)) {
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dev_err(dev, "unsupported data-lanes property size\n");
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return -EINVAL;
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}
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ret = dev_read_u32_array(dev, "data-lanes", priv->lanes,
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priv->num_lanes);
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if (ret) {
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dev_err(dev, "failed to read data-lanes property\n");
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return ret;
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}
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}
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ret = reset_get_by_name(dev, "phy", &priv->p30phy);
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if (ret) {
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dev_err(dev, "no phy reset control specified\n");
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return ret;
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}
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ret = clk_get_bulk(dev, &priv->clks);
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if (ret) {
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dev_err(dev, "failed to get clocks\n");
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return ret;
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}
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return 0;
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}
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static struct phy_ops rochchip_p3phy_ops = {
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.init = rochchip_p3phy_init,
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.exit = rochchip_p3phy_exit,
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};
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static const struct udevice_id rockchip_p3phy_of_match[] = {
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{
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.compatible = "rockchip,rk3568-pcie3-phy",
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.data = (ulong)&rk3568_ops,
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},
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{
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.compatible = "rockchip,rk3588-pcie3-phy",
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.data = (ulong)&rk3588_ops,
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},
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{ },
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};
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U_BOOT_DRIVER(rockchip_pcie3phy) = {
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.name = "rockchip_pcie3phy",
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.id = UCLASS_PHY,
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.of_match = rockchip_p3phy_of_match,
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.ops = &rochchip_p3phy_ops,
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.probe = rockchip_p3phy_probe,
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.priv_auto = sizeof(struct rockchip_p3phy_priv),
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};
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