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https://github.com/AsahiLinux/u-boot
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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
195 lines
5.2 KiB
C
195 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* MCF520x Internal Memory Map
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*
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* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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#ifndef __IMMAP_520X__
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#define __IMMAP_520X__
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#define MMAP_SCM1 (CFG_SYS_MBAR + 0x00000000)
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#define MMAP_XBS (CFG_SYS_MBAR + 0x00004000)
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#define MMAP_FBCS (CFG_SYS_MBAR + 0x00008000)
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#define MMAP_FEC0 (CFG_SYS_MBAR + 0x00030000)
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#define MMAP_SCM2 (CFG_SYS_MBAR + 0x00040000)
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#define MMAP_EDMA (CFG_SYS_MBAR + 0x00044000)
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#define MMAP_INTC0 (CFG_SYS_MBAR + 0x00048000)
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#define MMAP_INTCACK (CFG_SYS_MBAR + 0x00054000)
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#define MMAP_I2C (CFG_SYS_MBAR + 0x00058000)
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#define MMAP_QSPI (CFG_SYS_MBAR + 0x0005C000)
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#define MMAP_UART0 (CFG_SYS_MBAR + 0x00060000)
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#define MMAP_UART1 (CFG_SYS_MBAR + 0x00064000)
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#define MMAP_UART2 (CFG_SYS_MBAR + 0x00068000)
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#define MMAP_DTMR0 (CFG_SYS_MBAR + 0x00070000)
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#define MMAP_DTMR1 (CFG_SYS_MBAR + 0x00074000)
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#define MMAP_DTMR2 (CFG_SYS_MBAR + 0x00078000)
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#define MMAP_DTMR3 (CFG_SYS_MBAR + 0x0007C000)
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#define MMAP_PIT0 (CFG_SYS_MBAR + 0x00080000)
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#define MMAP_PIT1 (CFG_SYS_MBAR + 0x00084000)
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#define MMAP_EPORT0 (CFG_SYS_MBAR + 0x00088000)
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#define MMAP_WDOG (CFG_SYS_MBAR + 0x0008C000)
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#define MMAP_PLL (CFG_SYS_MBAR + 0x00090000)
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#define MMAP_RCM (CFG_SYS_MBAR + 0x000A0000)
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#define MMAP_CCM (CFG_SYS_MBAR + 0x000A0004)
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#define MMAP_GPIO (CFG_SYS_MBAR + 0x000A4000)
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#define MMAP_SDRAM (CFG_SYS_MBAR + 0x000A8000)
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#include <asm/coldfire/crossbar.h>
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#include <asm/coldfire/edma.h>
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#include <asm/coldfire/eport.h>
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#include <asm/coldfire/flexbus.h>
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#include <asm/coldfire/intctrl.h>
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#include <asm/coldfire/qspi.h>
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/* System Controller Module */
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typedef struct scm1 {
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u32 mpr; /* 0x00 Master Privilege */
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u32 rsvd1[7];
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u32 pacra; /* 0x20 Peripheral Access Ctrl A */
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u32 pacrb; /* 0x24 Peripheral Access Ctrl B */
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u32 pacrc; /* 0x28 Peripheral Access Ctrl C */
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u32 pacrd; /* 0x2C Peripheral Access Ctrl D */
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u32 rsvd2[4];
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u32 pacre; /* 0x40 Peripheral Access Ctrl E */
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u32 pacrf; /* 0x44 Peripheral Access Ctrl F */
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u32 rsvd3[3];
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u32 bmt; /* 0x50 bus monitor */
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} scm1_t;
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typedef struct scm2 {
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u8 rsvd1[19]; /* 0x00 - 0x12 */
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u8 wcr; /* 0x13 */
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u16 rsvd2; /* 0x14 - 0x15 */
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u16 cwcr; /* 0x16 */
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u8 rsvd3[3]; /* 0x18 - 0x1A */
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u8 cwsr; /* 0x1B */
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u8 rsvd4[3]; /* 0x1C - 0x1E */
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u8 scmisr; /* 0x1F */
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u8 rsvd5[79]; /* 0x20 - 0x6F */
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u32 cfadr; /* 0x70 */
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u8 rsvd7; /* 0x74 */
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u8 cfier; /* 0x75 */
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u8 cfloc; /* 0x76 */
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u8 cfatr; /* 0x77 */
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u32 rsvd8; /* 0x78 - 0x7B */
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u32 cfdtr; /* 0x7C */
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} scm2_t;
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/* Chip configuration module */
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typedef struct rcm {
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u8 rcr;
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u8 rsr;
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} rcm_t;
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typedef struct ccm_ctrl {
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u16 ccr; /* 0x00 Chip Cfg */
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u16 res1; /* 0x02 */
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u16 rcon; /* 0x04 Reset Cfg */
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u16 cir; /* 0x06 Chip ID */
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} ccm_t;
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/* GPIO port */
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typedef struct gpio_ctrl {
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/* Port Output Data */
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u8 podr_busctl; /* 0x00 */
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u8 podr_be; /* 0x01 */
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u8 podr_cs; /* 0x02 */
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u8 podr_feci2c; /* 0x03 */
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u8 podr_qspi; /* 0x04 */
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u8 podr_timer; /* 0x05 */
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u8 podr_uart; /* 0x06 */
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u8 podr_fech; /* 0x07 */
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u8 podr_fecl; /* 0x08 */
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u8 res01[3]; /* 0x9 - 0x0B */
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/* Port Data Direction */
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u8 pddr_busctl; /* 0x0C */
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u8 pddr_be; /* 0x0D */
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u8 pddr_cs; /* 0x0E */
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u8 pddr_feci2c; /* 0x0F */
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u8 pddr_qspi; /* 0x10*/
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u8 pddr_timer; /* 0x11 */
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u8 pddr_uart; /* 0x12 */
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u8 pddr_fech; /* 0x13 */
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u8 pddr_fecl; /* 0x14 */
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u8 res02[5]; /* 0x15 - 0x19 */
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/* Port Data Direction */
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u8 ppdr_cs; /* 0x1A */
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u8 ppdr_feci2c; /* 0x1B */
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u8 ppdr_qspi; /* 0x1C */
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u8 ppdr_timer; /* 0x1D */
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u8 ppdr_uart; /* 0x1E */
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u8 ppdr_fech; /* 0x1F */
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u8 ppdr_fecl; /* 0x20 */
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u8 res03[3]; /* 0x21 - 0x23 */
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/* Port Clear Output Data */
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u8 pclrr_busctl; /* 0x24 */
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u8 pclrr_be; /* 0x25 */
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u8 pclrr_cs; /* 0x26 */
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u8 pclrr_feci2c; /* 0x27 */
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u8 pclrr_qspi; /* 0x28 */
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u8 pclrr_timer; /* 0x29 */
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u8 pclrr_uart; /* 0x2A */
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u8 pclrr_fech; /* 0x2B */
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u8 pclrr_fecl; /* 0x2C */
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u8 res04[3]; /* 0x2D - 0x2F */
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/* Pin Assignment */
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u8 par_busctl; /* 0x30 */
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u8 par_be; /* 0x31 */
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u8 par_cs; /* 0x32 */
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u8 par_feci2c; /* 0x33 */
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u8 par_qspi; /* 0x34 */
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u8 par_timer; /* 0x35 */
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u16 par_uart; /* 0x36 */
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u8 par_fec; /* 0x38 */
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u8 par_irq; /* 0x39 */
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/* Mode Select Control */
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/* Drive Strength Control */
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u8 mscr_fb; /* 0x3A */
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u8 mscr_sdram; /* 0x3B */
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u8 dscr_i2c; /* 0x3C */
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u8 dscr_misc; /* 0x3D */
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u8 dscr_fec; /* 0x3E */
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u8 dscr_uart; /* 0x3F */
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u8 dscr_qspi; /* 0x40 */
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} gpio_t;
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/* SDRAM controller */
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typedef struct sdram_ctrl {
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u32 mode; /* 0x00 Mode/Extended Mode */
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u32 ctrl; /* 0x04 Ctrl */
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u32 cfg1; /* 0x08 Cfg 1 */
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u32 cfg2; /* 0x0C Cfg 2 */
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u32 res1[64]; /* 0x10 - 0x10F */
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u32 cs0; /* 0x110 Chip Select 0 Cfg */
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u32 cs1; /* 0x114 Chip Select 1 Cfg */
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} sdram_t;
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/* Clock Module */
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typedef struct pll_ctrl {
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u8 odr; /* 0x00 Output divider */
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u8 rsvd1;
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u8 cr; /* 0x02 Control */
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u8 rsvd2;
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u8 mdr; /* 0x04 Modulation Divider */
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u8 rsvd3;
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u8 fdr; /* 0x06 Feedback Divider */
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u8 rsvd4;
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} pll_t;
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/* Watchdog registers */
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typedef struct wdog_ctrl {
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u16 cr; /* 0x00 Control */
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u16 mr; /* 0x02 Modulus */
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u16 cntr; /* 0x04 Count */
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u16 sr; /* 0x06 Service */
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} wdog_t;
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#endif /* __IMMAP_520X__ */
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