mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
2af181b53e
R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING CFG, TCHAN CFG and RCHAN CFG address ranges. Note that these registers are present within respective IPs but are not populated in Linux DT nodes (as they are configured via TISCI APIs) and hence are added to -u-boot.dtsi for now. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Link: https://lore.kernel.org/r/20210607141753.28796-6-vigneshr@ti.com
217 lines
3 KiB
Text
217 lines
3 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &timer1;
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};
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aliases {
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ethernet0 = &cpsw_port1;
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spi0 = &ospi0;
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spi1 = &ospi1;
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remoteproc0 = &mcu_r5fss0_core0;
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remoteproc1 = &mcu_r5fss0_core1;
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remoteproc2 = &main_r5fss0_core0;
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remoteproc3 = &main_r5fss0_core1;
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remoteproc4 = &main_r5fss1_core0;
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remoteproc5 = &main_r5fss1_core1;
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remoteproc6 = &c66_0;
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remoteproc7 = &c66_1;
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remoteproc8 = &c71_0;
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i2c0 = &wkup_i2c0;
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i2c1 = &mcu_i2c0;
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i2c2 = &mcu_i2c1;
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i2c3 = &main_i2c0;
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};
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};
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&cbass_main{
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u-boot,dm-spl;
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main-navss {
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u-boot,dm-spl;
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};
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};
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&cbass_mcu_wakeup {
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u-boot,dm-spl;
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timer1: timer@40400000 {
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compatible = "ti,omap5430-timer";
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reg = <0x0 0x40400000 0x0 0x80>;
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ti,timer-alwon;
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clock-frequency = <250000000>;
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u-boot,dm-spl;
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};
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mcu-navss {
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u-boot,dm-spl;
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ringacc@2b800000 {
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reg = <0x0 0x2b800000 0x0 0x400000>,
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<0x0 0x2b000000 0x0 0x400000>,
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<0x0 0x28590000 0x0 0x100>,
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<0x0 0x2a500000 0x0 0x40000>,
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<0x0 0x28440000 0x0 0x40000>;
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reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
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u-boot,dm-spl;
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};
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dma-controller@285c0000 {
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reg = <0x0 0x285c0000 0x0 0x100>,
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<0x0 0x284c0000 0x0 0x4000>,
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<0x0 0x2a800000 0x0 0x40000>,
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<0x0 0x284a0000 0x0 0x4000>,
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<0x0 0x2aa00000 0x0 0x40000>,
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<0x0 0x28400000 0x0 0x2000>;
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reg-names = "gcfg", "rchan", "rchanrt", "tchan",
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"tchanrt", "rflow";
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u-boot,dm-spl;
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};
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};
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chipid@43000014 {
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u-boot,dm-spl;
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};
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};
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&secure_proxy_main {
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u-boot,dm-spl;
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};
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&dmsc {
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u-boot,dm-spl;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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u-boot,dm-spl;
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};
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};
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&k3_pds {
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u-boot,dm-spl;
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};
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&k3_clks {
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u-boot,dm-spl;
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};
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&k3_reset {
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u-boot,dm-spl;
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};
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&wkup_pmx0 {
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u-boot,dm-spl;
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};
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&main_pmx0 {
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u-boot,dm-spl;
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};
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&main_uart0 {
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u-boot,dm-spl;
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};
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&mcu_uart0 {
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u-boot,dm-spl;
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};
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&main_sdhci0 {
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u-boot,dm-spl;
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};
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&main_sdhci1 {
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u-boot,dm-spl;
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};
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&main_usbss0_pins_default {
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u-boot,dm-spl;
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};
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&usbss0 {
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u-boot,dm-spl;
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ti,usb2-only;
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};
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&usb0 {
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dr_mode = "peripheral";
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u-boot,dm-spl;
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};
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&mcu_cpsw {
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reg = <0x0 0x46000000 0x0 0x200000>,
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<0x0 0x40f00200 0x0 0x2>;
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reg-names = "cpsw_nuss", "mac_efuse";
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/delete-property/ ranges;
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cpsw-phy-sel@40f04040 {
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compatible = "ti,am654-cpsw-phy-sel";
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reg= <0x0 0x40f04040 0x0 0x4>;
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reg-names = "gmii-sel";
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};
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};
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&main_mmc1_pins_default {
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u-boot,dm-spl;
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};
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&wkup_i2c0_pins_default {
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u-boot,dm-spl;
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};
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&wkup_i2c0 {
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u-boot,dm-spl;
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};
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&main_i2c0 {
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u-boot,dm-spl;
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};
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&main_i2c0_pins_default {
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u-boot,dm-spl;
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};
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&exp2 {
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u-boot,dm-spl;
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};
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&mcu_fss0_ospi0_pins_default {
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u-boot,dm-spl;
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};
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&fss {
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u-boot,dm-spl;
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};
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&ospi0 {
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u-boot,dm-spl;
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flash@0 {
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u-boot,dm-spl;
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};
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};
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&ospi1 {
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u-boot,dm-spl;
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flash@0 {
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u-boot,dm-spl;
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};
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};
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&mcu_fss0_ospi1_pins_default {
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u-boot,dm-spl;
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};
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&main_r5fss0 {
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ti,cluster-mode = <0>;
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};
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&main_r5fss1 {
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ti,cluster-mode = <0>;
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};
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