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https://github.com/AsahiLinux/u-boot
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a7ba32d480
The device trees for these boards describe PCI I/O as starting from address zero from the device's perspective. Placing I/O elsewhere may cause problems with certain PCI boards, and may cause problems with Linux. Signed-off-by: Scott Wood <scottwood@freescale.com>
604 lines
17 KiB
C
604 lines
17 KiB
C
/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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#define CONFIG_MPC83XX 1 /* MPC83XX family */
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#define CONFIG_MPC837X 1 /* MPC837X CPU specific */
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#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
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/*
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* System Clock Setup
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*/
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#ifdef CONFIG_PCISLAVE
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#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
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#else
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#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
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#endif
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#ifndef CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_CLK_FREQ 66000000
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#endif
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/*
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* Hardware Reset Configuration Word
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* if CLKIN is 66MHz, then
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* CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
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*/
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#define CFG_HRCW_LOW (\
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HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
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HRCWL_DDR_TO_SCB_CLK_1X1 |\
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HRCWL_SVCOD_DIV_2 |\
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HRCWL_CSB_TO_CLKIN_6X1 |\
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HRCWL_CORE_TO_CSB_1_5X1)
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#ifdef CONFIG_PCISLAVE
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#define CFG_HRCW_HIGH (\
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HRCWH_PCI_AGENT |\
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HRCWH_PCI1_ARBITER_DISABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0XFFF00100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_RL_EXT_LEGACY |\
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HRCWH_TSEC1M_IN_RGMII |\
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HRCWH_TSEC2M_IN_RGMII |\
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HRCWH_BIG_ENDIAN |\
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HRCWH_LDP_CLEAR)
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#else
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#define CFG_HRCW_HIGH (\
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HRCWH_PCI_HOST |\
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HRCWH_PCI1_ARBITER_ENABLE |\
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HRCWH_CORE_ENABLE |\
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HRCWH_FROM_0X00000100 |\
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HRCWH_BOOTSEQ_DISABLE |\
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HRCWH_SW_WATCHDOG_DISABLE |\
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HRCWH_ROM_LOC_LOCAL_16BIT |\
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HRCWH_RL_EXT_LEGACY |\
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HRCWH_TSEC1M_IN_RGMII |\
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HRCWH_TSEC2M_IN_RGMII |\
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HRCWH_BIG_ENDIAN |\
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HRCWH_LDP_CLEAR)
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#endif
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/* Arbiter Configuration Register */
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#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
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#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
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/* System Priority Control Register */
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#define CFG_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
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/*
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* IP blocks clock configuration
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*/
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#define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
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#define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
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#define CFG_SCCR_SATACM SCCR_SATACM_1 /* CSB:SATA[0:3] = 1:1 */
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/*
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* System IO Config
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*/
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#define CFG_SICRH 0x00000000
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#define CFG_SICRL 0x00000000
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/*
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* Output Buffer Impedance
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*/
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#define CFG_OBIR 0x31100000
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#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
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#define CONFIG_BOARD_EARLY_INIT_R
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/*
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* IMMR new address
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*/
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#define CFG_IMMR 0xE0000000
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/*
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* DDR Setup
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*/
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#define CFG_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CFG_SDRAM_BASE CFG_DDR_BASE
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#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
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#define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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#define CFG_83XX_DDR_USES_CS0
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#define CFG_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */
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#undef CONFIG_DDR_ECC /* support DDR ECC function */
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#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
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#if defined(CONFIG_SPD_EEPROM)
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#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
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#else
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/*
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* Manually set up DDR parameters
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* WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
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* consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
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*/
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#define CFG_DDR_SIZE 512 /* MB */
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#define CFG_DDR_CS0_BNDS 0x0000001f
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#define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \
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| 0x00010000 /* ODT_WR to CSn */ \
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| CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 )
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/* 0x80010202 */
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#define CFG_DDR_TIMING_3 0x00000000
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#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
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| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
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| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
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| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
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| ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
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| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
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| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
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| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
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/* 0x00620802 */
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#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
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| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
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| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
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| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
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| (13 << TIMING_CFG1_REFREC_SHIFT ) \
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| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
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| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
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| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
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/* 0x3935d322 */
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#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \
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| ( 6 << TIMING_CFG2_CPO_SHIFT ) \
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| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
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| ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
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| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
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| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
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| ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) )
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/* 0x131088c8 */
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#define CFG_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \
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| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
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/* 0x03E00100 */
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#define CFG_DDR_SDRAM_CFG 0x43000000
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#define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
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#define CFG_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \
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| ( 0x1432 << SDRAM_MODE_SD_SHIFT ) )
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/* ODT 150ohm CL=3, AL=1 on SDRAM */
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#define CFG_DDR_MODE2 0x00000000
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#endif
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/*
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* Memory test
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*/
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#undef CFG_DRAM_TEST /* memory test, takes time */
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#define CFG_MEMTEST_START 0x00040000 /* memtest region */
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#define CFG_MEMTEST_END 0x00140000
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/*
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* The reserved memory
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*/
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
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#define CFG_RAMBOOT
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#else
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#undef CFG_RAMBOOT
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#endif
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/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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/*
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* Initial RAM Base Address Setup
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*/
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#define CFG_INIT_RAM_LOCK 1
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#define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8)
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#define CFG_LBC_LBCR 0x00000000
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/*
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* FLASH on the Local Bus
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*/
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#define CFG_FLASH_CFI /* use the Common Flash Interface */
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#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
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#define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */
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#define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */
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#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */
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#define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
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#define CFG_BR0_PRELIM ( CFG_FLASH_BASE /* Flash Base address */ \
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| (2 << BR_PS_SHIFT) /* 16 bit port size */ \
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| BR_V ) /* valid */
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#define CFG_OR0_PRELIM ( (~(CFG_FLASH_SIZE - 1) << 20) \
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| OR_UPM_XAM \
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| OR_GPCM_CSNT \
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| OR_GPCM_ACS_0b11 \
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| OR_GPCM_XACS \
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| OR_GPCM_SCY_15 \
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| OR_GPCM_TRLX \
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| OR_GPCM_EHTR \
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| OR_GPCM_EAD )
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/* 0xFE000FF7 */
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_SECT 256 /* max sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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/*
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* BCSR on the Local Bus
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*/
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#define CFG_BCSR 0xF8000000
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#define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */
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#define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
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#define CFG_BR1_PRELIM (CFG_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */
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#define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
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/*
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* NAND Flash on the Local Bus
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*/
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#define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */
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#define CFG_BR3_PRELIM ( CFG_NAND_BASE \
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| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
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| BR_PS_8 /* Port Size = 8 bit */ \
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| BR_MS_FCM /* MSEL = FCM */ \
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| BR_V ) /* valid */
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#define CFG_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \
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| OR_FCM_CSCT \
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| OR_FCM_CST \
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| OR_FCM_CHT \
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| OR_FCM_SCY_1 \
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| OR_FCM_TRLX \
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| OR_FCM_EHTR )
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/* 0xFFFF8396 */
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#define CFG_LBLAWBAR3_PRELIM CFG_NAND_BASE
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#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
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/*
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* Serial Port
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*/
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK get_bus_freq(0)
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
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#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
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/* Use the HUSH parser */
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#define CFG_HUSH_PARSER
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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/* Pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define CONFIG_OF_STDOUT_VIA_ALIAS 1
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/* I2C */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CONFIG_FSL_I2C
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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#define CFG_I2C2_OFFSET 0x3100
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/*
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* Config on-board RTC
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*/
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#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
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#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CFG_PCI_MEM_BASE 0x80000000
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#define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE
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#define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */
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#define CFG_PCI_MMIO_BASE 0x90000000
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#define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE
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#define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */
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#define CFG_PCI_IO_BASE 0x00000000
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#define CFG_PCI_IO_PHYS 0xE0300000
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#define CFG_PCI_IO_SIZE 0x100000 /* 1M */
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#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE
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#define CFG_PCI_SLV_MEM_BUS 0x00000000
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#define CFG_PCI_SLV_MEM_SIZE 0x80000000
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#ifdef CONFIG_PCI
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#define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */
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#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#undef CONFIG_EEPRO100
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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#endif /* CONFIG_PCI */
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#endif
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/*
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* TSEC
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*/
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#define CONFIG_TSEC_ENET /* TSEC ethernet support */
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#define CFG_TSEC1_OFFSET 0x24000
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#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
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#define CFG_TSEC2_OFFSET 0x25000
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#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
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/*
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* TSEC ethernet configuration
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*/
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC1"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 3
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "eTSEC1"
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/*
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* Environment
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*/
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#ifndef CFG_RAMBOOT
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
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#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
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#define CFG_ENV_SIZE 0x2000
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#else
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#define CFG_NO_FLASH 1 /* Flash is not usable now */
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#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
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#define CFG_ENV_SIZE 0x2000
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_DATE
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#if defined(CFG_RAMBOOT)
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#undef CONFIG_CMD_ENV
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#undef CONFIG_CMD_LOADS
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#endif
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#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
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|
|
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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|
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|
/*
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* Miscellaneous configurable options
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|
*/
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|
#define CFG_LONGHELP /* undef to save memory */
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|
#define CFG_LOAD_ADDR 0x2000000 /* default load address */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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|
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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|
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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|
#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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|
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
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|
|
|
/*
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|
* For booting Linux, the board info and command line data
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|
* have to be in the first 8 MB of memory, since this is
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|
* the maximum mapped by the Linux kernel during initialization.
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|
*/
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|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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|
|
|
/*
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|
* Core HID Setup
|
|
*/
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|
#define CFG_HID0_INIT 0x000000000
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|
#define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK
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|
#define CFG_HID2 HID2_HBE
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|
|
|
/*
|
|
* MMU Setup
|
|
*/
|
|
|
|
/* DDR: cache cacheable */
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|
#define CFG_SDRAM_LOWER CFG_SDRAM_BASE
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|
#define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000)
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|
|
|
#define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
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|
#define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
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|
#define CFG_DBAT0L CFG_IBAT0L
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|
#define CFG_DBAT0U CFG_IBAT0U
|
|
|
|
#define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
|
|
#define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT1L CFG_IBAT1L
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|
#define CFG_DBAT1U CFG_IBAT1U
|
|
|
|
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
|
|
#define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \
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|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
#define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT2L CFG_IBAT2L
|
|
#define CFG_DBAT2U CFG_IBAT2U
|
|
|
|
/* BCSR: cache-inhibit and guarded */
|
|
#define CFG_IBAT3L (CFG_BCSR | BATL_PP_10 | \
|
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
#define CFG_IBAT3U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT3L CFG_IBAT3L
|
|
#define CFG_DBAT3U CFG_IBAT3U
|
|
|
|
/* FLASH: icache cacheable, but dcache-inhibit and guarded */
|
|
#define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
|
|
#define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \
|
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
#define CFG_DBAT4U CFG_IBAT4U
|
|
|
|
/* Stack in dcache: cacheable, no memory coherence */
|
|
#define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10)
|
|
#define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT5L CFG_IBAT5L
|
|
#define CFG_DBAT5U CFG_IBAT5U
|
|
|
|
#ifdef CONFIG_PCI
|
|
/* PCI MEM space: cacheable */
|
|
#define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
|
|
#define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT6L CFG_IBAT6L
|
|
#define CFG_DBAT6U CFG_IBAT6U
|
|
/* PCI MMIO space: cache-inhibit and guarded */
|
|
#define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \
|
|
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
|
|
#define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
|
|
#define CFG_DBAT7L CFG_IBAT7L
|
|
#define CFG_DBAT7U CFG_IBAT7U
|
|
#else
|
|
#define CFG_IBAT6L (0)
|
|
#define CFG_IBAT6U (0)
|
|
#define CFG_IBAT7L (0)
|
|
#define CFG_IBAT7U (0)
|
|
#define CFG_DBAT6L CFG_IBAT6L
|
|
#define CFG_DBAT6U CFG_IBAT6U
|
|
#define CFG_DBAT7L CFG_IBAT7L
|
|
#define CFG_DBAT7U CFG_IBAT7U
|
|
#endif
|
|
|
|
/*
|
|
* Internal Definitions
|
|
*
|
|
* Boot Flags
|
|
*/
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
|
|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
|
#endif
|
|
|
|
/*
|
|
* Environment Configuration
|
|
*/
|
|
|
|
#define CONFIG_ENV_OVERWRITE
|
|
|
|
#if defined(CONFIG_TSEC_ENET)
|
|
#define CONFIG_HAS_ETH0
|
|
#define CONFIG_ETHADDR 00:E0:0C:00:83:79
|
|
#define CONFIG_HAS_ETH1
|
|
#define CONFIG_ETH1ADDR 00:E0:0C:00:83:78
|
|
#endif
|
|
|
|
#define CONFIG_BAUDRATE 115200
|
|
|
|
#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
|
|
|
|
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
|
|
#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"netdev=eth0\0" \
|
|
"consoledev=ttyS0\0" \
|
|
"ramdiskaddr=1000000\0" \
|
|
"ramdiskfile=ramfs.83xx\0" \
|
|
"fdtaddr=400000\0" \
|
|
"fdtfile=mpc8379_mds.dtb\0" \
|
|
""
|
|
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=$serverip:$rootpath " \
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr - $fdtaddr"
|
|
|
|
#define CONFIG_RAMBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $fdtaddr $fdtfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
|
|
|
|
#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
|
|
|
|
#endif /* __CONFIG_H */
|