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cd93d625fd
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
318 lines
7.8 KiB
C
318 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Freescale i.MX28 GPIO control code
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*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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* on behalf of DENX Software Engineering GmbH
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*/
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#include <common.h>
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#include <log.h>
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#include <malloc.h>
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#include <linux/bitops.h>
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#include <linux/errno.h>
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#include <asm/io.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/imx-regs.h>
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#if defined(CONFIG_MX23)
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#define PINCTRL_BANKS 3
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#define PINCTRL_DOUT(n) (0x0500 + ((n) * 0x10))
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#define PINCTRL_DIN(n) (0x0600 + ((n) * 0x10))
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#define PINCTRL_DOE(n) (0x0700 + ((n) * 0x10))
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#define PINCTRL_PIN2IRQ(n) (0x0800 + ((n) * 0x10))
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#define PINCTRL_IRQEN(n) (0x0900 + ((n) * 0x10))
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#define PINCTRL_IRQSTAT(n) (0x0c00 + ((n) * 0x10))
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#elif defined(CONFIG_MX28)
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#define PINCTRL_BANKS 5
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#define PINCTRL_DOUT(n) (0x0700 + ((n) * 0x10))
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#define PINCTRL_DIN(n) (0x0900 + ((n) * 0x10))
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#define PINCTRL_DOE(n) (0x0b00 + ((n) * 0x10))
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#define PINCTRL_PIN2IRQ(n) (0x1000 + ((n) * 0x10))
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#define PINCTRL_IRQEN(n) (0x1100 + ((n) * 0x10))
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#define PINCTRL_IRQSTAT(n) (0x1400 + ((n) * 0x10))
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#else
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#error "Please select CONFIG_MX23 or CONFIG_MX28"
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#endif
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#define GPIO_INT_FALL_EDGE 0x0
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#define GPIO_INT_LOW_LEV 0x1
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#define GPIO_INT_RISE_EDGE 0x2
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#define GPIO_INT_HIGH_LEV 0x3
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#define GPIO_INT_LEV_MASK (1 << 0)
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#define GPIO_INT_POL_MASK (1 << 1)
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void mxs_gpio_init(void)
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{
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int i;
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for (i = 0; i < PINCTRL_BANKS; i++) {
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writel(0, MXS_PINCTRL_BASE + PINCTRL_PIN2IRQ(i));
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writel(0, MXS_PINCTRL_BASE + PINCTRL_IRQEN(i));
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/* Use SCT address here to clear the IRQSTAT bits */
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writel(0xffffffff, MXS_PINCTRL_BASE + PINCTRL_IRQSTAT(i) + 8);
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}
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}
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#if !CONFIG_IS_ENABLED(DM_GPIO)
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int gpio_get_value(unsigned gpio)
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{
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uint32_t bank = PAD_BANK(gpio);
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uint32_t offset = PINCTRL_DIN(bank);
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struct mxs_register_32 *reg =
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(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
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return (readl(®->reg) >> PAD_PIN(gpio)) & 1;
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}
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void gpio_set_value(unsigned gpio, int value)
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{
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uint32_t bank = PAD_BANK(gpio);
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uint32_t offset = PINCTRL_DOUT(bank);
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struct mxs_register_32 *reg =
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(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
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if (value)
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writel(1 << PAD_PIN(gpio), ®->reg_set);
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else
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writel(1 << PAD_PIN(gpio), ®->reg_clr);
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}
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int gpio_direction_input(unsigned gpio)
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{
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uint32_t bank = PAD_BANK(gpio);
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uint32_t offset = PINCTRL_DOE(bank);
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struct mxs_register_32 *reg =
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(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
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writel(1 << PAD_PIN(gpio), ®->reg_clr);
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return 0;
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}
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int gpio_direction_output(unsigned gpio, int value)
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{
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uint32_t bank = PAD_BANK(gpio);
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uint32_t offset = PINCTRL_DOE(bank);
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struct mxs_register_32 *reg =
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(struct mxs_register_32 *)(MXS_PINCTRL_BASE + offset);
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gpio_set_value(gpio, value);
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writel(1 << PAD_PIN(gpio), ®->reg_set);
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return 0;
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}
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int gpio_request(unsigned gpio, const char *label)
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{
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if (PAD_BANK(gpio) >= PINCTRL_BANKS)
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return -1;
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return 0;
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}
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int gpio_free(unsigned gpio)
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{
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return 0;
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}
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int name_to_gpio(const char *name)
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{
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unsigned bank, pin;
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char *end;
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bank = simple_strtoul(name, &end, 10);
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if (!*end || *end != ':')
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return bank;
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pin = simple_strtoul(end + 1, NULL, 10);
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return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT);
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}
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#else /* DM_GPIO */
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#include <dm.h>
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#include <asm/gpio.h>
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#include <dt-structs.h>
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#include <asm/arch/gpio.h>
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#define MXS_MAX_GPIO_PER_BANK 32
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#ifdef CONFIG_MX28
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#define dtd_fsl_imx_gpio dtd_fsl_imx28_gpio
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#else /* CONFIG_MX23 */
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#define dtd_fsl_imx_gpio dtd_fsl_imx23_gpio
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* According to i.MX28 Reference Manual:
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* 'i.MX28 Applications Processor Reference Manual, Rev. 1, 2010'
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* The i.MX28 has following number of GPIOs available:
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* Bank 0: 0-28 -> 29 PINS
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* Bank 1: 0-31 -> 32 PINS
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* Bank 2: 0-27 -> 28 PINS
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* Bank 3: 0-30 -> 31 PINS
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* Bank 4: 0-20 -> 21 PINS
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*/
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struct mxs_gpio_platdata {
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_fsl_imx_gpio dtplat;
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#endif
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unsigned int bank;
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int gpio_ranges;
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};
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struct mxs_gpio_priv {
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unsigned int bank;
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};
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static int mxs_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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struct mxs_gpio_priv *priv = dev_get_priv(dev);
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struct mxs_register_32 *reg =
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(struct mxs_register_32 *)(MXS_PINCTRL_BASE +
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PINCTRL_DIN(priv->bank));
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return (readl(®->reg) >> offset) & 1;
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}
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static int mxs_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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struct mxs_gpio_priv *priv = dev_get_priv(dev);
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struct mxs_register_32 *reg =
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(struct mxs_register_32 *)(MXS_PINCTRL_BASE +
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PINCTRL_DOUT(priv->bank));
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if (value)
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writel(BIT(offset), ®->reg_set);
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else
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writel(BIT(offset), ®->reg_clr);
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return 0;
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}
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static int mxs_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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struct mxs_gpio_priv *priv = dev_get_priv(dev);
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struct mxs_register_32 *reg =
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(struct mxs_register_32 *)(MXS_PINCTRL_BASE +
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PINCTRL_DOE(priv->bank));
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writel(BIT(offset), ®->reg_clr);
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return 0;
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}
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static int mxs_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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struct mxs_gpio_priv *priv = dev_get_priv(dev);
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struct mxs_register_32 *reg =
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(struct mxs_register_32 *)(MXS_PINCTRL_BASE +
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PINCTRL_DOE(priv->bank));
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mxs_gpio_set_value(dev, offset, value);
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writel(BIT(offset), ®->reg_set);
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return 0;
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}
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static int mxs_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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struct mxs_gpio_priv *priv = dev_get_priv(dev);
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struct mxs_register_32 *reg =
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(struct mxs_register_32 *)(MXS_PINCTRL_BASE +
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PINCTRL_DOE(priv->bank));
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bool is_output = !!(readl(®->reg) >> offset);
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return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
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}
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static const struct dm_gpio_ops gpio_mxs_ops = {
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.direction_input = mxs_gpio_direction_input,
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.direction_output = mxs_gpio_direction_output,
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.get_value = mxs_gpio_get_value,
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.set_value = mxs_gpio_set_value,
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.get_function = mxs_gpio_get_function,
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};
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static int mxs_gpio_probe(struct udevice *dev)
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{
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struct mxs_gpio_platdata *plat = dev_get_platdata(dev);
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struct mxs_gpio_priv *priv = dev_get_priv(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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char name[16], *str;
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#if CONFIG_IS_ENABLED(OF_PLATDATA)
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struct dtd_fsl_imx_gpio *dtplat = &plat->dtplat;
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priv->bank = (unsigned int)dtplat->reg[0];
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uc_priv->gpio_count = dtplat->gpio_ranges[3];
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#else
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priv->bank = (unsigned int)plat->bank;
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uc_priv->gpio_count = plat->gpio_ranges;
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#endif
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snprintf(name, sizeof(name), "GPIO%d_", priv->bank);
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str = strdup(name);
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if (!str)
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return -ENOMEM;
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uc_priv->bank_name = str;
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debug("%s: %s: %d pins base: 0x%x\n", __func__, uc_priv->bank_name,
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uc_priv->gpio_count, priv->bank);
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return 0;
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}
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#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
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static int mxs_ofdata_to_platdata(struct udevice *dev)
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{
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struct mxs_gpio_platdata *plat = dev->platdata;
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struct fdtdec_phandle_args args;
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int node = dev_of_offset(dev);
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int ret;
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plat->bank = devfdt_get_addr(dev);
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if (plat->bank == FDT_ADDR_T_NONE) {
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printf("%s: No 'reg' property defined!\n", __func__);
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return -EINVAL;
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}
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ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges",
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NULL, 3, 0, &args);
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if (ret)
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printf("%s: 'gpio-ranges' not defined - using default!\n",
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__func__);
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plat->gpio_ranges = ret == 0 ? args.args[2] : MXS_MAX_GPIO_PER_BANK;
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return 0;
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}
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static const struct udevice_id mxs_gpio_ids[] = {
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{ .compatible = "fsl,imx23-gpio" },
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{ .compatible = "fsl,imx28-gpio" },
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{ }
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};
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#endif
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U_BOOT_DRIVER(gpio_mxs) = {
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#ifdef CONFIG_MX28
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.name = "fsl_imx28_gpio",
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#else /* CONFIG_MX23 */
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.name = "fsl_imx23_gpio",
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#endif
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.id = UCLASS_GPIO,
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.ops = &gpio_mxs_ops,
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.probe = mxs_gpio_probe,
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.priv_auto_alloc_size = sizeof(struct mxs_gpio_priv),
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.platdata_auto_alloc_size = sizeof(struct mxs_gpio_platdata),
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#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
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.of_match = mxs_gpio_ids,
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.ofdata_to_platdata = mxs_ofdata_to_platdata,
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#endif
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};
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#endif /* DM_GPIO */
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