mirror of
https://github.com/AsahiLinux/u-boot
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0ed384fd2f
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NOR namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
404 lines
14 KiB
C
404 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017, 2019-2021 NXP
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* Copyright 2015 Freescale Semiconductor
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*/
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#ifndef __LS2_QDS_H
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#define __LS2_QDS_H
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#include "ls2080a_common.h"
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#ifdef CONFIG_FSL_QSPI
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#define CONFIG_SYS_I2C_IFDR_DIV 0x7e
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#endif
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#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
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#define COUNTER_FREQUENCY_REAL (get_board_sys_clk()/4)
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#define SPD_EEPROM_ADDRESS1 0x51
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#define SPD_EEPROM_ADDRESS2 0x52
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#define SPD_EEPROM_ADDRESS3 0x53
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#define SPD_EEPROM_ADDRESS4 0x54
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#define SPD_EEPROM_ADDRESS5 0x55
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#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */
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#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
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#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
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#define CFG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
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#define CFG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
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#define CONFIG_SYS_NOR0_CSPR \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR0_CSPR_EARLY \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR1_CSPR \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR1_CSPR_EARLY \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CFG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
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#define CFG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
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FTIM0_NOR_TEADC(0x5) | \
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FTIM0_NOR_TEAHC(0x5))
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#define CFG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
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FTIM1_NOR_TRAD_NOR(0x1a) |\
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FTIM1_NOR_TSEQRAD_NOR(0x13))
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#define CFG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
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FTIM2_NOR_TCH(0x4) | \
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FTIM2_NOR_TWPH(0x0E) | \
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FTIM2_NOR_TWP(0x1c))
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#define CFG_SYS_NOR_FTIM3 0x04000000
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#define CONFIG_SYS_IFC_CCR 0x01000000
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#ifdef CONFIG_MTD_NOR_FLASH
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
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CONFIG_SYS_FLASH_BASE + 0x40000000}
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#endif
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#define CFG_SYS_NAND_CSPR_EXT (0x0)
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#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
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| CSPR_MSEL_NAND /* MSEL = NAND */ \
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| CSPR_V)
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#define CFG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
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#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
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| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
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| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
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/* ONFI NAND Flash mode0 Timing Params */
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#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x07) | \
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FTIM0_NAND_TWH(0x0a))
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#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0x0e) | \
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FTIM1_NAND_TRP(0x18))
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#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
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FTIM2_NAND_TREH(0x0a) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CFG_SYS_NAND_FTIM3 0x0
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#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define QIXIS_LBMAP_SWITCH 0x06
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#define QIXIS_LBMAP_MASK 0x0f
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#define QIXIS_LBMAP_SHIFT 0
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#define QIXIS_LBMAP_DFLTBANK 0x00
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#define QIXIS_LBMAP_ALTBANK 0x04
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#define QIXIS_LBMAP_NAND 0x09
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#define QIXIS_LBMAP_SD 0x00
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#define QIXIS_LBMAP_QSPI 0x0f
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#define QIXIS_RST_CTL_RESET 0x31
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#define QIXIS_RCW_SRC_NAND 0x107
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#define QIXIS_RCW_SRC_SD 0x40
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#define QIXIS_RCW_SRC_QSPI 0x62
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#define QIXIS_RST_FORCE_MEM 0x01
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#define CONFIG_SYS_CSPR3_EXT (0x0)
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#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_GPCM \
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| CSPR_V)
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#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_GPCM \
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| CSPR_V)
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#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024)
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#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12)
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/* QIXIS Timing parameters for IFC CS3 */
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#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
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FTIM0_GPCM_TEADC(0x0e) | \
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FTIM0_GPCM_TEAHC(0x0e))
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#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
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FTIM1_GPCM_TRAD(0x3f))
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#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
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FTIM2_GPCM_TCH(0xf) | \
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FTIM2_GPCM_TWP(0x3E))
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#define CONFIG_SYS_CS3_FTIM3 0x0
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#if defined(CONFIG_SPL)
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#if defined(CONFIG_NAND_BOOT)
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY
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#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY
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#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR
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#define CONFIG_SYS_AMASK2 CFG_SYS_NOR_AMASK_EARLY
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#define CONFIG_SYS_AMASK2_FINAL CFG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR2 CFG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR0_EXT CFG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
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#define CFG_SYS_NAND_U_BOOT_SIZE (640 * 1024)
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#endif
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#else
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
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#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK0 CFG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CFG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
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#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
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#define CONFIG_SYS_AMASK1 CFG_SYS_NOR_AMASK_EARLY
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#define CONFIG_SYS_AMASK1_FINAL CFG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CFG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NOR_FTIM3
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#define CONFIG_SYS_CSPR2_EXT CFG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CFG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK2 CFG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR2 CFG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS2_FTIM0 CFG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 CFG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 CFG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 CFG_SYS_NAND_FTIM3
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#endif
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#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
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/*
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* I2C
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*/
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#define I2C_MUX_PCA_ADDR 0x77
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#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
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/* I2C bus multiplexer */
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#define I2C_MUX_CH_DEFAULT 0x8
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/* SPI */
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/*
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* Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure.
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* If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0
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* If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1
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*/
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#define FSL_QIXIS_BRDCFG9_QSPI 0x1
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/*
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* RTC configuration
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*/
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#define RTC
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#define CONFIG_RTC_DS3231 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68
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/* Initial environment variables */
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#undef CONFIG_EXTRA_ENV_SETTINGS
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#ifdef CONFIG_NXP_ESBC
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"loadaddr=0x80100000\0" \
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"kernel_addr=0x100000\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xa0000000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0x581000000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"mcmemsize=0x40000000\0" \
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"mcinitcmd=esbc_validate 0x580640000;" \
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"esbc_validate 0x580680000;" \
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"fsl_mc start mc 0x580a00000" \
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" 0x580e00000 \0"
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#else
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#ifdef CONFIG_TFABOOT
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#define SD_MC_INIT_CMD \
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"mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
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"mmc read 0x80e00000 0x7000 0x800;" \
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"fsl_mc start mc 0x80a00000 0x80e00000\0"
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#define IFC_MC_INIT_CMD \
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"fsl_mc start mc 0x580a00000" \
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" 0x580e00000 \0"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"loadaddr=0x80100000\0" \
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"loadaddr_sd=0x90100000\0" \
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"kernel_addr=0x581000000\0" \
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"kernel_addr_sd=0x8000\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xa0000000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0x581000000\0" \
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"kernel_start_sd=0x8000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"kernel_size_sd=0x14000\0" \
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"load_addr=0xa0000000\0" \
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"kernelheader_addr=0x580600000\0" \
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"kernelheader_addr_r=0x80200000\0" \
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"kernelheader_size=0x40000\0" \
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"BOARD=ls2088aqds\0" \
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"mcmemsize=0x70000000 \0" \
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"scriptaddr=0x80000000\0" \
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"scripthdraddr=0x80080000\0" \
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IFC_MC_INIT_CMD \
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BOOTENV \
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"boot_scripts=ls2088aqds_boot.scr\0" \
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"boot_script_hdr=hdr_ls2088aqds_bs.out\0" \
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"scan_dev_for_boot_part=" \
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"part list ${devtype} ${devnum} devplist; " \
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"env exists devplist || setenv devplist 1; " \
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"for distro_bootpart in ${devplist}; do " \
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"if fstype ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"bootfstype; then " \
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"run scan_dev_for_boot; " \
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"fi; " \
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"done\0" \
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"boot_a_script=" \
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"load ${devtype} ${devnum}:${distro_bootpart} " \
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"${scriptaddr} ${prefix}${script}; " \
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"env exists secureboot && load ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"${scripthdraddr} ${prefix}${boot_script_hdr} " \
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"&& esbc_validate ${scripthdraddr};" \
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"source ${scriptaddr}\0" \
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"nor_bootcmd=echo Trying load from nor..;" \
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"cp.b $kernel_addr $load_addr " \
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"$kernel_size ; env exists secureboot && " \
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"cp.b $kernelheader_addr $kernelheader_addr_r " \
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"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
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"bootm $load_addr#$BOARD\0" \
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"sd_bootcmd=echo Trying load from SD ..;" \
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"mmcinfo; mmc read $load_addr " \
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"$kernel_addr_sd $kernel_size_sd && " \
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"bootm $load_addr#$BOARD\0"
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#elif defined(CONFIG_SD_BOOT)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"loadaddr=0x90100000\0" \
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"kernel_addr=0x800\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xa0000000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0x8000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x14000\0" \
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"mcinitcmd=mmcinfo;mmc read 0x80a00000 0x5000 0x1000;" \
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"mmc read 0x80e00000 0x7000 0x800;" \
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"fsl_mc start mc 0x80a00000 0x80e00000\0" \
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"mcmemsize=0x70000000 \0"
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#else
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"loadaddr=0x80100000\0" \
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"kernel_addr=0x100000\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xa0000000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0x581000000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"mcmemsize=0x40000000\0" \
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"mcinitcmd=fsl_mc start mc 0x580a00000" \
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" 0x580e00000 \0"
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#endif /* CONFIG_TFABOOT */
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#endif /* CONFIG_NXP_ESBC */
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#ifdef CONFIG_TFABOOT
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#define BOOT_TARGET_DEVICES(func) \
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func(USB, usb, 0) \
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func(MMC, mmc, 0) \
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func(SCSI, scsi, 0) \
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func(DHCP, dhcp, na)
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#include <config_distro_bootcmd.h>
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#define SD_BOOTCOMMAND \
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"env exists mcinitcmd && env exists secureboot "\
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"&& mmcinfo && mmc read $load_addr 0x3600 0x800 " \
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"&& esbc_validate $load_addr; " \
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"env exists mcinitcmd && run mcinitcmd " \
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"&& mmc read 0x80d00000 0x6800 0x800 " \
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"&& fsl_mc lazyapply dpl 0x80d00000; " \
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"run distro_bootcmd;run sd_bootcmd; " \
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"env exists secureboot && esbc_halt;"
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#define IFC_NOR_BOOTCOMMAND \
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"env exists mcinitcmd && env exists secureboot "\
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"&& esbc_validate 0x5806C0000; env exists mcinitcmd "\
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"&& fsl_mc lazyapply dpl 0x580d00000;" \
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"run distro_bootcmd;run nor_bootcmd; " \
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"env exists secureboot && esbc_halt;"
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#endif
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#if defined(CONFIG_FSL_MC_ENET)
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#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
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#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
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#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
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#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
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#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
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#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
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#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
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#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
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#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
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#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
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#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
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#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
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#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
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#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
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#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
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#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
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#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
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#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
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#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
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#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
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#endif
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#include <asm/fsl_secure_boot.h>
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#endif /* __LS2_QDS_H */
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