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https://github.com/AsahiLinux/u-boot
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91092132ba
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS_NS16550 namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
131 lines
3.2 KiB
C
131 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <console.h>
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#include <env_internal.h>
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#include <init.h>
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#include <malloc.h>
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#include <ns16550.h>
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#include <nand.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <spi_flash.h>
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#include <asm/global_data.h>
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#include "../common/sleep.h"
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#include "../common/spl.h"
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DECLARE_GLOBAL_DATA_PTR;
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phys_size_t get_effective_memsize(void)
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{
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return CONFIG_SYS_L3_SIZE;
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}
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#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
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void board_init_f(ulong bootflag)
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{
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u32 plat_ratio, sys_clk, uart_clk;
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#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
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u32 porsr1, pinctl;
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u32 svr = get_svr();
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#endif
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ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
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#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
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if (IS_SVR_REV(svr, 1, 0)) {
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/*
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* There is T1040 SoC issue where NOR, FPGA are inaccessible
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* during NAND boot because IFC signals > IFC_AD7 are not
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* enabled. This workaround changes RCW source to make all
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* signals enabled.
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*/
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porsr1 = in_be32(&gur->porsr1);
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pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
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| 0x24800000);
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out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
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pinctl);
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}
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#endif
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/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
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memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
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/* Update GD pointer */
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gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
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#ifdef CONFIG_DEEP_SLEEP
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/* disable the console if boot from deep sleep */
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if (is_warm_boot())
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fsl_dp_disable_console();
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#endif
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/* compiler optimization barrier needed for GCC >= 3.4 */
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__asm__ __volatile__("" : : : "memory");
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console_init_f();
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/* initialize selected port with appropriate baud rate */
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sys_clk = get_board_sys_clk();
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plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
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uart_clk = sys_clk * plat_ratio / 2;
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ns16550_init((struct ns16550 *)CFG_SYS_NS16550_COM1,
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uart_clk / 16 / CONFIG_BAUDRATE);
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relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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struct bd_info *bd;
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bd = (struct bd_info *)(gd + sizeof(gd_t));
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memset(bd, 0, sizeof(struct bd_info));
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gd->bd = bd;
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arch_cpu_init();
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get_clocks();
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mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
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CONFIG_SPL_RELOC_MALLOC_SIZE);
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gd->flags |= GD_FLG_FULL_MALLOC_INIT;
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_initialize(bd);
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#endif
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/* relocate environment function pointers etc. */
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#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_MMC) || \
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defined(CONFIG_ENV_IS_IN_SPI_FLASH)
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#ifdef CONFIG_SPL_NAND_BOOT
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)SPL_ENV_ADDR);
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#endif
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)SPL_ENV_ADDR);
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#endif
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#ifdef CONFIG_SPL_SPI_BOOT
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fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)SPL_ENV_ADDR);
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#endif
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gd->env_addr = (ulong)(SPL_ENV_ADDR);
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gd->env_valid = ENV_VALID;
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#endif
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i2c_init_all();
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puts("\n\n");
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dram_init();
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#ifdef CONFIG_SPL_MMC_BOOT
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mmc_boot();
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#elif defined(CONFIG_SPL_SPI_BOOT)
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fsl_spi_boot();
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#elif defined(CONFIG_SPL_NAND_BOOT)
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nand_boot();
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#endif
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}
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