mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 18:28:55 +00:00
0b42fdca2d
Synchronise device tree with linux v6.1-rc3.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Tested-By: Tim Harvey <tharvey@gateworks.com> #imx8m{m,n,p}-venice-*
205 lines
5 KiB
Text
205 lines
5 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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/dts-v1/;
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#include <dt-bindings/leds/leds-pca9532.h>
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#include <dt-bindings/pwm/pwm.h>
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#include "imx8mp-phycore-som.dtsi"
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/ {
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model = "PHYTEC phyBOARD-Pollux i.MX8MP";
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compatible = "phytec,imx8mp-phyboard-pollux-rdk",
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"phytec,imx8mp-phycore-som", "fsl,imx8mp";
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chosen {
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stdout-path = &uart1;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0x1>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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enet-phy-lane-no-swap;
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};
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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};
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leds@62 {
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compatible = "nxp,pca9533";
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reg = <0x62>;
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led1 {
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type = <PCA9532_TYPE_LED>;
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};
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led2 {
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type = <PCA9532_TYPE_LED>;
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};
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led3 {
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type = <PCA9532_TYPE_LED>;
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};
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};
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};
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&snvs_pwrkey {
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status = "okay";
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};
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/* debug console */
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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/* SD-Card */
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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bus-width = <4>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
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MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
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MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
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MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
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MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
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MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
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MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
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MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
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MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
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MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
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MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
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MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
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MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
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MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
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MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
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MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
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>;
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};
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pinctrl_i2c2_gpio: i2c2gpiogrp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
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MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
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MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
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>;
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};
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pinctrl_usdhc2_pins: usdhc2-gpiogrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
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>;
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};
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};
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