u-boot/arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
Tim Harvey 9bf0cbf396 arm: dts: imx8mm-venice-gw7901: add dsa phy handles to u-boot dtsi
The upstream Linux DSA drivers do not require phy-handle nodes in
the DSA ports yet the U-Boot DSA drivers do. Add a phy-handle and
the mdio nodes to the u-boot.dtsi file so that future dts file
syncrhonization between Linux and U-Boot don't break networking.

Fixes: 24a7a3c1c0 ("imx8mm: synchronise device tree with linux")
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2022-09-20 18:30:02 +02:00

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2.7 KiB
Text

// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2020 Gateworks Corporation
*/
#include "imx8mm-venice-u-boot.dtsi"
&gpio1 {
uart1_rs422 {
gpio-hog;
output-high;
gpios = <0 GPIO_ACTIVE_HIGH>;
line-name = "uart1_rs422#";
};
uart1rs485 {
gpio-hog;
output-high;
gpios = <3 GPIO_ACTIVE_HIGH>;
line-name = "uart1_rs485#";
};
uart1rs232 {
gpio-hog;
output-high;
gpios = <5 GPIO_ACTIVE_HIGH>;
line-name = "uart1_rs232#";
};
dig1in {
gpio-hog;
input;
gpios = <6 GPIO_ACTIVE_HIGH>;
line-name = "dig1_in";
};
dig1out {
gpio-hog;
output-low;
gpios = <7 GPIO_ACTIVE_HIGH>;
line-name = "dig1_out";
};
};
&gpio4 {
uart3_rs232 {
gpio-hog;
output-high;
gpios = <6 GPIO_ACTIVE_HIGH>;
line-name = "uart3_rs232#";
};
uart3_rs422 {
gpio-hog;
output-high;
gpios = <7 GPIO_ACTIVE_HIGH>;
line-name = "uart3_rs422#";
};
uart3_rs485 {
gpio-hog;
output-high;
gpios = <8 GPIO_ACTIVE_HIGH>;
line-name = "uart3_rs485#";
};
uart4_rs485 {
gpio-hog;
output-high;
gpios = <27 GPIO_ACTIVE_HIGH>;
line-name = "uart4_rs485#";
};
sim1det {
gpio-hog;
input;
gpios = <29 GPIO_ACTIVE_HIGH>;
line-name = "sim1_det";
};
sim2det {
gpio-hog;
input;
gpios = <30 GPIO_ACTIVE_HIGH>;
line-name = "sim2_det";
};
};
&gpio5 {
dig2out {
gpio-hog;
output-low;
gpios = <3 GPIO_ACTIVE_HIGH>;
line-name = "dig2_out";
};
dig2in {
gpio-hog;
input;
gpios = <4 GPIO_ACTIVE_HIGH>;
line-name = "dig2_in";
};
sim2sel {
gpio-hog;
output-low;
gpios = <5 GPIO_ACTIVE_HIGH>;
line-name = "sim2_sel";
};
uart4_rs232 {
gpio-hog;
output-high;
gpios = <10 GPIO_ACTIVE_HIGH>;
line-name = "uart4_rs232#";
};
uart4_rs422 {
gpio-hog;
output-high;
gpios = <13 GPIO_ACTIVE_HIGH>;
line-name = "uart4_rs422#";
};
};
&fec1 {
phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <1>;
};
&switch {
ports {
#address-cells = <1>;
#size-cells = <0>;
lan1: port@0 {
phy-handle = <&sw_phy0>;
};
lan2: port@1 {
phy-handle = <&sw_phy1>;
};
lan3: port@2 {
phy-handle = <&sw_phy2>;
};
lan4: port@3 {
phy-handle = <&sw_phy3>;
};
};
mdios {
#address-cells = <1>;
#size-cells = <0>;
mdio@0 {
reg = <0>;
compatible = "microchip,ksz-mdio";
#address-cells = <1>;
#size-cells = <0>;
sw_phy0: ethernet-phy@0 {
reg = <0x0>;
};
sw_phy1: ethernet-phy@1 {
reg = <0x1>;
};
sw_phy2: ethernet-phy@2 {
reg = <0x2>;
};
sw_phy3: ethernet-phy@3 {
reg = <0x3>;
};
};
};
};
&pinctrl_fec1 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};