mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-19 09:43:08 +00:00
77b11f7604
As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
437 lines
18 KiB
Text
437 lines
18 KiB
Text
SoC overview
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1. LS1043A
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2. LS1088A
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3. LS2080A
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4. LS1012A
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5. LS1046A
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6. LS2088A
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7. LS2081A
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8. LX2160A
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9. LS1028A
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10. LX2162A
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LS1043A
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---------
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The LS1043A integrated multicore processor combines four ARM Cortex-A53
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processor cores with datapath acceleration optimized for L2/3 packet
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processing, single pass security offload and robust traffic management
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and quality of service.
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The LS1043A SoC includes the following function and features:
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- Four 64-bit ARM Cortex-A53 CPUs
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- 1 MB unified L2 Cache
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- One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
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support
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration the
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the following functions:
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- Packet parsing, classification, and distribution (FMan)
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- Queue management for scheduling, packet sequencing, and congestion
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management (QMan)
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- Hardware buffer management for buffer allocation and de-allocation (BMan)
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- Cryptography acceleration (SEC)
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- Ethernet interfaces by FMan
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- Up to 1 x 10GBase-R supporting 10G interface
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- Up to 1 x QSGMII
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- Up to 4 x SGMII supporting 1000Mbps
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- Up to 2 x SGMII supporting 2500Mbps
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- Up to 2 x RGMII supporting 1000Mbps
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- High-speed peripheral interfaces
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- Three PCIe 2.0 controllers, one supporting x4 operation
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- One serial ATA (SATA 3.0) controllers
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- Additional peripheral interfaces
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- Three high-speed USB 3.0 controllers with integrated PHY
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- Enhanced secure digital host controller (eSDXC/eMMC)
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- Quad Serial Peripheral Interface (QSPI) Controller
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- Serial peripheral interface (SPI) controller
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- Four I2C controllers
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- Two DUARTs
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- Integrated flash controller supporting NAND and NOR flash
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- QorIQ platform's trust architecture 2.1
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LS1088A
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--------
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The QorIQ LS1088A processor is built on the Layerscape
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architecture combining eight ARM A53 processor cores
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with advanced, high-performance datapath acceleration
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and networks, peripheral interfaces required for
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networking, wireless infrastructure, and general-purpose
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embedded applications.
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LS1088A is compliant with the Layerscape Chassis Generation 3.
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Features summary:
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- 8 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
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- Cores are in 2 cluster of 4-cores each
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- 1MB L2 - Cache per cluster
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- Cache coherent interconnect (CCI-400)
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- 1 64-bit DDR4 SDRAM memory controller with ECC
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- Data path acceleration architecture 2.0 (DPAA2)
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- 4-Lane 10GHz SerDes comprising of WRIOP
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- 4-Lane 10GHz SerDes comprising of PCI, SATA, uQE(TDM/HLDC/UART)
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- Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
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- QSPI, SPI, IFC2.0 supporting NAND, NOR flash
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- 3 PCIe3.0 , 1 SATA3.0, 2 USB3.0, 1 SDXC, 2 DUARTs etc
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- 2 DUARTs
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- 4 I2C, GPIO
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- Thermal monitor unit(TMU)
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- 4 Flextimers and 1 generic timer
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- Support for hardware virtualization and partitioning enforcement
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- QorIQ platform's trust architecture 3.0
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- Service processor (SP) provides pre-boot initialization and secure-boot
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capabilities
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LS2080A
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--------
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The LS2080A integrated multicore processor combines eight ARM Cortex-A57
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processor cores with high-performance data path acceleration logic and network
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and peripheral bus interfaces required for networking, telecom/datacom,
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wireless infrastructure, and mil/aerospace applications.
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The LS2080A SoC includes the following function and features:
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- Eight 64-bit ARM Cortex-A57 CPUs
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- 1 MB platform cache with ECC
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- Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
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- One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
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the AIOP
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- Data path acceleration architecture (DPAA2) incorporating acceleration for
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the following functions:
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- Packet parsing, classification, and distribution (WRIOP)
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- Queue and Hardware buffer management for scheduling, packet sequencing, and
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congestion management, buffer allocation and de-allocation (QBMan)
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- Cryptography acceleration (SEC) at up to 10 Gbps
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- RegEx pattern matching acceleration (PME) at up to 10 Gbps
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- Decompression/compression acceleration (DCE) at up to 20 Gbps
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- Accelerated I/O processing (AIOP) at up to 20 Gbps
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- QDMA engine
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- 16 SerDes lanes at up to 10.3125 GHz
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- Ethernet interfaces
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- Up to eight 10 Gbps Ethernet MACs
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- Up to eight 1 / 2.5 Gbps Ethernet MACs
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- High-speed peripheral interfaces
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- Four PCIe 3.0 controllers, one supporting SR-IOV
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- Additional peripheral interfaces
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- Two serial ATA (SATA 3.0) controllers
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- Two high-speed USB 3.0 controllers with integrated PHY
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- Enhanced secure digital host controller (eSDXC/eMMC)
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- Serial peripheral interface (SPI) controller
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- Quad Serial Peripheral Interface (QSPI) Controller
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- Four I2C controllers
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- Two DUARTs
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- Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
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- Support for hardware virtualization and partitioning enforcement
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- QorIQ platform's trust architecture 3.0
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- Service processor (SP) provides pre-boot initialization and secure-boot
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capabilities
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LS1012A
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--------
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The LS1012A features an advanced 64-bit ARM v8 Cortex-
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A53 processor, with 32 KB of parity protected L1-I cache,
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32 KB of ECC protected L1-D cache, as well as 256 KB of
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ECC protected L2 cache.
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The LS1012A SoC includes the following function and features:
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- One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
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- ARM v8 cryptography extensions
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- One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
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16-/8-bit operation (no ECC support)
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- ARM core-link CCI-400 cache coherent interconnect
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- Packet Forwarding Engine (PFE)
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- Cryptography acceleration (SEC)
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- Ethernet interfaces supported by PFE:
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- One Configurable x3 SerDes:
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Two Serdes PLLs supported for usage by any SerDes data lane
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Support for up to 6 GBaud operation
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- High-speed peripheral interfaces:
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- One PCI Express Gen2 controller, supporting x1 operation
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- One serial ATA (SATA Gen 3.0) controller
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- One USB 3.0/2.0 controller with integrated PHY
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- One USB 2.0 controller with ULPI interface. .
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- Additional peripheral interfaces:
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- One quad serial peripheral interface (QuadSPI) controller
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- One serial peripheral interface (SPI) controller
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- Two enhanced secure digital host controllers
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- Two I2C controllers
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- One 16550 compliant DUART (two UART interfaces)
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- Two general purpose IOs (GPIO)
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- Two FlexTimers
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- Five synchronous audio interfaces (SAI)
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- Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
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- Single-source clocking solution enabling generation of core, platform,
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DDR, SerDes, and USB clocks from a single external crystal and internal
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crystaloscillator
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- Thermal monitor unit (TMU) with +/- 3C accuracy
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- Two WatchDog timers
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- ARM generic timer
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- QorIQ platform's trust architecture 2.1
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LS1046A
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--------
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The LS1046A integrated multicore processor combines four ARM Cortex-A72
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processor cores with datapath acceleration optimized for L2/3 packet
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processing, single pass security offload and robust traffic management
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and quality of service.
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The LS1046A SoC includes the following function and features:
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- Four 64-bit ARM Cortex-A72 CPUs
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- 2 MB unified L2 Cache
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- One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
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support
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration the
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the following functions:
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- Packet parsing, classification, and distribution (FMan)
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- Queue management for scheduling, packet sequencing, and congestion
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management (QMan)
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- Hardware buffer management for buffer allocation and de-allocation (BMan)
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- Cryptography acceleration (SEC)
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- Two Configurable x4 SerDes
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- Two PLLs per four-lane SerDes
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- Support for 10G operation
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- Ethernet interfaces by FMan
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- Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10)
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- Up to 1 x QSGMII (MAC 5, 6, 10, 1)
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- Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
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- Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
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- Up to 2 x RGMII supporting 1000Mbps (MAC 3, 4)
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- High-speed peripheral interfaces
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- Three PCIe 3.0 controllers, one supporting x4 operation
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- One serial ATA (SATA 3.0) controllers
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- Additional peripheral interfaces
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- Three high-speed USB 3.0 controllers with integrated PHY
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- Enhanced secure digital host controller (eSDXC/eMMC)
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- Quad Serial Peripheral Interface (QSPI) Controller
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- Serial peripheral interface (SPI) controller
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- Four I2C controllers
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- Two DUARTs
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- Integrated flash controller (IFC) supporting NAND and NOR flash
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- QorIQ platform's trust architecture 2.1
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LS2088A
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--------
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The LS2088A integrated multicore processor combines eight ARM Cortex-A72
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processor cores with high-performance data path acceleration logic and network
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and peripheral bus interfaces required for networking, telecom/datacom,
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wireless infrastructure, and mil/aerospace applications.
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The LS2088A SoC includes the following function and features:
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- Eight 64-bit ARM Cortex-A72 CPUs
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- 1 MB platform cache with ECC
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- Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
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- One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
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the AIOP
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- Data path acceleration architecture (DPAA2) incorporating acceleration for
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the following functions:
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- Packet parsing, classification, and distribution (WRIOP)
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- Queue and Hardware buffer management for scheduling, packet sequencing, and
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congestion management, buffer allocation and de-allocation (QBMan)
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- Cryptography acceleration (SEC) at up to 10 Gbps
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- RegEx pattern matching acceleration (PME) at up to 10 Gbps
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- Decompression/compression acceleration (DCE) at up to 20 Gbps
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- Accelerated I/O processing (AIOP) at up to 20 Gbps
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- QDMA engine
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- 16 SerDes lanes at up to 10.3125 GHz
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- Ethernet interfaces
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- Up to eight 10 Gbps Ethernet MACs
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- Up to eight 1 / 2.5 Gbps Ethernet MACs
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- High-speed peripheral interfaces
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- Four PCIe 3.0 controllers, one supporting SR-IOV
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- Additional peripheral interfaces
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- Two serial ATA (SATA 3.0) controllers
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- Two high-speed USB 3.0 controllers with integrated PHY
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- Enhanced secure digital host controller (eSDXC/eMMC)
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- Serial peripheral interface (SPI) controller
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- Quad Serial Peripheral Interface (QSPI) Controller
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- Four I2C controllers
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- Two DUARTs
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- Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
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- Support for hardware virtualization and partitioning enforcement
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- QorIQ platform's trust architecture 3.0
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- Service processor (SP) provides pre-boot initialization and secure-boot
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capabilities
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LS2088A SoC has 3 more similar SoC personalities
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1)LS2048A, few difference w.r.t. LS2088A:
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a) Four 64-bit ARM v8 Cortex-A72 CPUs
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2)LS2084A, few difference w.r.t. LS2088A:
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a) No AIOP
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b) No 32-bit DDR3 SDRAM memory
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c) 5 * 1/10G + 5 *1G WRIOP
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d) No L2 switch
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3)LS2044A, few difference w.r.t. LS2084A:
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a) Four 64-bit ARM v8 Cortex-A72 CPUs
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LS2081A
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--------
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LS2081A is 40-pin derivative of LS2084A.
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So feature-wise it is same as LS2084A.
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Refer to LS2084A(LS2088A) section above for details.
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It has one more similar SoC personality
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1)LS2041A, few difference w.r.t. LS2081A:
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a) Four 64-bit ARM v8 Cortex-A72 CPUs
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LX2160A
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--------
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The QorIQ LX2160A processor is built in the 16FFC process on
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the Layerscape architecture combining sixteen ARM A72 processor
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cores with advanced, high-performance datapath acceleration and
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network, peripheral interfaces required for networking, wireless
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infrastructure, storage, and general-purpose embedded applications.
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LX2160A is compliant with the Layerscape Chassis Generation 3.2.
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The LX2160A SoC includes the following function and features:
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Sixteen 32-bit / 64-bit ARM v8 A72 CPUs
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Cache Coherent Interconnect Fabric (CCN508 aka “Eliot”)
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Two 64-bit 3.2GT/s DDR4 SDRAM memory controllers with ECC.
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Data path acceleration architecture (DPAA2)
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24 Serdes lanes at up to 25 GHz
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Ethernet interfaces
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Single WRIOP tile supporting 130Gbps using 18 MACs
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Support for 10G-SXGMII (aka USXGMII).
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Support for SGMII (and 1000Base-KX)
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Support for 10GBase-R (and 10GBase-KR)
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Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G).
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Support for XLAUI (and 40GBase-KR4) for 40G.
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Support for two RGMII parallel interfaces.
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Energy efficient Ethernet support (802.3az)
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IEEE 1588 support.
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High-speed peripheral interfaces
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Two PCIe Gen 4.0 8-lane controllers supporting SR-IOV,
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Four PCIe Gen 4.0 4-lane controllers.
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Four serial ATA (SATA 3.0) controllers.
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Two USB 3.0 controllers with integrated PHY
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Two Enhanced secure digital host controllers
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Two Controller Area Network (CAN) modules
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Flexible Serial peripheral interface (FlexSPI) controller.
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Three Serial peripheral interface (SPI) controllers.
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Eight I2C Controllers.
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Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports.
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General Purpose IO (GPIO)
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Support for hardware virtualization and partitioning (ARM MMU-500)
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Support for GIC (ARM GIC-500)
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QorIQ platform Trust Architecture 3.0
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One Secure WatchDog timer and one Non-Secure Watchdog timer.
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ARM Generic Timer
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Two Flextimers
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Debug supporting run control, data acquisition, high-speed trace,
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performance/event monitoring
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Thermal Monitor Unit (TMU) with +/- 2C accuracy
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Support for Voltage ID (VID) for yield improvement
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LX2160A SoC has 2 more similar SoC personalities
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1)LX2120A, few difference w.r.t. LX2160A:
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a) Twelve 64-bit ARM v8 Cortex-A72 CPUs
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2)LX2080A, few difference w.r.t. LX2160A:
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a) Eight 64-bit ARM v8 Cortex-A72 CPUs
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LS1028A
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--------
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The QorIQ LS1028A processor integrates two 64-bit Arm Cortex-A72 cores with
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a GPU and LCD controller, as well as two TSN-enabled Ethernet controllers and
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a TSNenabled 4-port switch.
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The high performance Cortex-A72 cores, performing above 16,000 CoreMarks,
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combined with 2.5 Gbit Ethernet, PCI express Gen 3.0, SATA 3.0, USB 3.0 and
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Octal/Quad SPI interfaces provide capabilities for a number of industrial and
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embedded applications. The device provides excellent integration with the
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new Time-Sensitive Networking standard, and enables a number of
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TSN applications.
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The LS1028A SoC includes the following function and features:
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- Two 64-bit ARM v8 A72 CPUs
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- Cache Coherent interconnect (CCI-400)
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- One 32-bit DDR3L/DDR4 SDRAM memory controller with ECC
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- eDP/Displayport interface
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- Graphics processing unit
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- One Configurable x4 SerDes
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- Ethernet interfaces
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- Non-switched: One Ethernet MAC supporting 2.5G, 1G, 100M, 10M, one
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ethernet MAC supporting 1G, 100M, 10M.
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- Switched: TSN IP to support four 2.5/1G interfaces.
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- None of the MACs support MACSEC
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- Support for RGMII, SGMII (and 1000Base-KX), SGMII 2.5x, QSGMII
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- Support for 10G-SXGMII and 10G-QXGMII.
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- Energy efficient Ethernet support (802.3az)
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- IEEE 1588 support
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- High-speed peripheral interfaces
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- Two PCIe 3.0 controllers, one supporting x4 operation
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- One serial ATA (SATA 3.0) controller
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- Additional peripheral interfaces
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- Two high-speed USB 2.0/3.0 controllers with integrated PHY each
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supporting host or device modes
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- Two Enhanced secure digital host controllers (SD/SDIO/eMMC)
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- Two Serial peripheral interface (SPI) controllers
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- Eight I2C controllers
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- Two UART controllers
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- Additional six Industrual UARTs (LPUART).
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- One FlexSPI controller
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- General Purpose IO (GPIO)
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- Two CAN-FD interfaces
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- Eight Flextimers with PWM I/O
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- Support for hardware virtualization and partitioning enforcement
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- Layerscape Trust Architecture
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- Service Processor (SP) provides pre-boot initialization and secure-boot
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capabilities
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LX2162A
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--------
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The QorIQ LX2162A processor is built on the Layerscape architecture
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combining sixteen ARM A72 processor cores with advanced, high-performance
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datapath acceleration and network, peripheral interfaces required for
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networking, wireless infrastructure, storage, and general-purpose embedded
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applications.
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LX2162A is compliant with the Layerscape Chassis Generation 3.2.
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The LX2162A SoC includes the following function and features:
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Sixteen 32-bit / 64-bit ARM v8 A72 CPUs
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Cache Coherent Interconnect Fabric (CCN508)
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One 64-bit 2.9GT/s DDR4 SDRAM memory controllers with ECC.
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Data path acceleration architecture (DPAA2)
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12 Serdes lanes at up to 25 GHz
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Ethernet interfaces
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Support for 10G-SXGMII (aka USXGMII).
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Support for SGMII (and 1000Base-KX)
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Support for 10GBase-R (and 10GBase-KR)
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Support for CAUI2 (50G) and 25G-AUI(25G).
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Support for XLAUI (and 40GBase-KR4) for 40G.
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Support for two RGMII parallel interfaces.
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Energy efficient Ethernet support (802.3az)
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IEEE 1588 support.
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High-speed peripheral interfaces
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One PCIe Gen 3.0 8-lane controllers supporting SR-IOV,
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Two PCIe Gen 3.0 4-lane controllers.
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Four serial ATA (SATA 3.0) controllers.
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One USB 3.0 controllers with integrated PHY
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Two Enhanced secure digital host controllers
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Two Controller Area Network (CAN) modules
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Flexible Serial peripheral interface (FlexSPI) controller.
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Three Serial peripheral interface (SPI) controllers.
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Eight I2C Controllers.
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Four PL011 UARTs supporting two 4-pin UART ports or four 2-pin UART ports.
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General Purpose IO (GPIO)
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Support for hardware virtualization and partitioning (ARM MMU-500)
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Support for GIC (ARM GIC-500)
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QorIQ platform Trust Architecture 3.0
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One Secure WatchDog timer and one Non-Secure Watchdog timer.
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ARM Generic Timer
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Two Flextimers
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Debug supporting run control, data acquisition, high-speed trace,
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performance/event monitoring
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Thermal Monitor Unit (TMU) with +/- 2C accuracy
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Support for Voltage ID (VID) for yield improvement
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LX2162A SoC has 2 more similar SoC personalities
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1)LX2122A, few difference w.r.t. LX2162A:
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a) Twelve 64-bit ARM v8 Cortex-A72 CPUs
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2)LX2082A, few difference w.r.t. LX2162A:
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a) Eight 64-bit ARM v8 Cortex-A72 CPUs
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