mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 10:30:32 +00:00
9973e3c614
This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> |
||
|---|---|---|
| .. | ||
| config.mk | ||
| hcu4.c | ||
| Makefile | ||
| README.txt | ||
| u-boot.lds | ||
HCU4 Configuration Details Memory Bank 0 -- Flash chip --------------------------- 0xfff00000 - 0xffffffff The flash chip is really only 512Kbytes, but the high address bit of the 1Meg region is ignored, so the flash is replicated through the region. Thus, this is consistent with a flash base address 0xfff80000. The placement at the end is to be consistent with reset behavior, where the processor itself initially uses this bus to load the branch vector and start running. On-Chip Memory -------------- 0xf4000000 - 0xf4000fff The 405GPr includes a 4K on-chip memory that can be placed however software chooses. I choose to place the memory at this address, to keep it out of the cachable areas. Internal Peripherals -------------------- 0xef600300 - 0xef6008ff These are scattered various peripherals internal to the PPC405GPr chip. Chip-Select 2: Flash Memory --------------------------- 0x70000000 Chip-Select 3: CAN Interface ---------------------------- 0x7800000 Chip-Select 4: IMC-bus standard ------------------------------- Our IO-Bus (slow version) Chip-Select 5: IMC-bus fast (inactive) -------------------------------------- Our IO-Bus (fast, but not yet use) Memory Bank 1 -- SDRAM ------------------------------------- 0x00000000 - 0x1ffffff # Default 32 MB