mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-27 13:33:40 +00:00
8bde7f776c
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
92 lines
2.9 KiB
C
92 lines
2.9 KiB
C
/*
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* (C) Copyright 2001
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* Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _W7O_H_
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#define _W7O_H_
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#include <config.h>
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/* IBM 405GP PowerPC GPIO registers */
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#define IBM405GP_GPIO0_OR 0xef600700L /* GPIO Output */
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#define IBM405GP_GPIO0_TCR 0xef600704L /* GPIO Three-State Control */
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#define IBM405GP_GPIO0_ODR 0xef600718L /* GPIO Open Drain */
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#define IBM405GP_GPIO0_IR 0xef60071cL /* GPIO Input */
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/* IBM 405GP DCRs */
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#define CPC0_CR0 0xb1 /* Chip control register 0 */
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/* LMG FPGA <=> CPU GPIO signals */
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#define LMG_XCV_INIT 0x10000000L
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#define LMG_XCV_PROG 0x04000000L
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#define LMG_XCV_DONE 0x00400000L
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#define LMG_XCV_CNFG_0 0x08000000L
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#define LMG_XCV_IRQ_0 0x0L
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/* LMC FPGA <=> CPU GPIO signals */
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#define LMC_XCV_INIT 0x00800000L
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#define LMC_XCV_PROG 0x40000000L
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#define LMC_XCV_DONE 0x01000000L
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#define LMC_XCV_CNFG_0 0x00004000L /* Shared with IRQ 0 */
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#define LMC_XCV_CNFG_1 0x00002000L /* Shared with IRQ 1 */
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#define LMC_XCV_CNFG_2 0x00001000L /* Shared with IRQ 2 */
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#define LMC_XCV_IRQ_0 0x00080000L /* Shared with GPIO 17 */
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#define LMC_XCV_IRQ_1 0x00040000L /* Shared with GPIO 18 */
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#define LMC_XCV_IRQ_3 0x00020000L /* Shared tiwht GPIO 19 */
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/*
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* Setup FPGA <=> GPIO mappings
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*/
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#if defined(CONFIG_W7OLMG)
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# define GPIO_XCV_INIT LMG_XCV_INIT
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# define GPIO_XCV_PROG LMG_XCV_PROG
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# define GPIO_XCV_DONE LMG_XCV_DONE
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# define GPIO_XCV_CNFG LMG_XCV_CNFG_0
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# define GPIO_XCV_IRQ LMG_XCV_IRQ_0
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# define GPIO_GPIO_1 0x40000000L
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# define GPIO_GPIO_6 0x02000000L
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# define GPIO_GPIO_7 0x01000000L
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# define GPIO_GPIO_8 0x00800000L
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#elif defined(CONFIG_W7OLMC)
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# define GPIO_XCV_INIT LMC_XCV_INIT
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# define GPIO_XCV_PROG LMC_XCV_PROG
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# define GPIO_XCV_DONE LMC_XCV_DONE
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# define GPIO_XCV_CNFG LMC_XCV_CNFG_0
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# define GPIO_XCV_IRQ LMC_XCV_IRQ_0
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#else
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# error "Unknown W7O board configuration"
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#endif
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/* Power On Self Tests */
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extern void post2(void);
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extern int test_led(void);
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extern int test_sdram(unsigned long size);
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extern void test_fpga(unsigned short *daddr);
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/* FGPA */
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extern int init_fpga(void);
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/* Misc */
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extern int temp_uart_init(void);
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extern void init_fsboot(void);
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#endif /* _W7O_H_ */
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