mirror of
https://github.com/AsahiLinux/u-boot
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134 lines
3.7 KiB
C
134 lines
3.7 KiB
C
/*
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* (C) Copyright 2001
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* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
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*
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* (C) Copyright 2002
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* Gregory E. Allen, gallen@arlut.utexas.edu
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* Matthew E. Karger, karger@arlut.utexas.edu
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* Applied Research Laboratories, The University of Texas at Austin
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <pci.h>
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#define SAVE_SZ 32
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int checkboard(void)
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{
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ulong busfreq = get_bus_freq(0);
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char buf[32];
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printf("Board: UTX8245 Local Bus at %s MHz\n", strmhz(buf, busfreq));
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return 0;
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}
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long int initdram(int board_type)
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{
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#if 1
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long size;
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long new_bank0_end;
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long mear1;
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long emear1;
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/*
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write_bat(IBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
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( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
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write_bat(DBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
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( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
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*/
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size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
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new_bank0_end = size - 1;
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mear1 = mpc824x_mpc107_getreg(MEAR1);
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emear1 = mpc824x_mpc107_getreg(EMEAR1);
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mear1 = (mear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
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emear1 = (emear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
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mpc824x_mpc107_setreg(MEAR1, mear1);
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mpc824x_mpc107_setreg(EMEAR1, emear1);
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return (size);
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#else
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return (CFG_MAX_RAM_SIZE);
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#endif
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}
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/*
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* Initialize PCI Devices, report devices found.
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*/
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static struct pci_config_table pci_utx8245_config_table[] = {
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#ifndef CONFIG_PCI_PNP
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0C, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0B, PCI_ANY_ID,
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pci_cfgfunc_config_device, { PCI_FIREWIRE_IOADDR,
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PCI_FIREWIRE_MEMADDR,
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PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
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#endif /*CONFIG_PCI_PNP*/
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{ }
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};
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static void pci_utx8245_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
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{
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if (PCI_DEV(dev) == 11)
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/* assign serial interrupt line 9 (int25) to FireWire */
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 25);
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else if (PCI_DEV(dev) == 12)
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/* assign serial interrupt line 8 (int24) to Ethernet */
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 24);
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else if (PCI_DEV(dev) == 14)
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/* assign serial interrupt line 0 (int16) to PMC slot 0 */
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 16);
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else if (PCI_DEV(dev) == 15)
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/* assign serial interrupt line 1 (int17) to PMC slot 1 */
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 17);
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}
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static struct pci_controller utx8245_hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_utx8245_config_table,
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fixup_irq: pci_utx8245_fixup_irq,
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write_byte: pci_hose_write_config_byte
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#endif /*CONFIG_PCI_PNP*/
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};
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void pci_init_board (void)
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{
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pci_mpc824x_init(&utx8245_hose);
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icache_enable();
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}
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