mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-28 05:53:54 +00:00
7205e4075d
add FAT support for IDE, SCSI and USB
* Patches by Gleb Natapov, 2 Sep 2003:
- cleanup of POST code for unsupported architectures
- MPC824x locks way0 of data cache for use as initial RAM;
this patch unlocks it after relocation to RAM and invalidates
the locked entries.
* Patch by Gleb Natapov, 30 Aug 2003:
new I2C driver for mpc107 bridge. Now works from flash.
* Patch by Dave Ellis, 11 Aug 2003:
- JFFS2: fix typo in common/cmd_jffs2.c
- JFFS2: fix CFG_JFFS2_SORT_FRAGMENTS option
- JFFS2: remove node version 0 warning
- JFFS2: accept JFFS2 PADDING nodes
- SXNI855T: add AM29LV800 support
- SXNI855T: move environment from EEPROM to flash
- SXNI855T: boot from JFFS2 in NOR or NAND flash
* Patch by Bill Hargen, 11 Aug 2003:
fixes for I2C on MPC8240
- fix i2c_write routine
- fix iprobe command
- eliminates use of global variables, plus dead code, cleanup.
183 lines
9 KiB
C
183 lines
9 KiB
C
/*
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* (C) Copyright 2001
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* Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/****************************************************************************
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* Global routines used for MIP405
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*****************************************************************************/
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#ifndef __ASSEMBLY__
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/*int switch_cs(unsigned char boot);*/
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extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
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void user_led0(unsigned char on);
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#endif
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/* timings */
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/* PLD (CS7) */
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#define PLD_BME 0 /* Burst disable */
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#define PLD_TWE 5 /* 5 * 30ns 120ns Waitstates (access=TWT+1+TH) */
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#define PLD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
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#define PLD_OEN 1 /* Cycles from CS low to OE low */
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#define PLD_WBN 1 /* Cycles from CS low to WE low */
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#define PLD_WBF 1 /* Cycles from WE high to CS high */
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#define PLD_TH 2 /* Number of hold cycles after transfer */
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#define PLD_RE 0 /* Ready disabled */
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#define PLD_SOR 1 /* Sample on Ready disabled */
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#define PLD_BEM 0 /* Byte Write only active on Write cycles */
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#define PLD_PEN 0 /* Parity disable */
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#define PLD_AP ((PLD_BME << 31) + (PLD_TWE << 23) + (PLD_CSN << 18) + (PLD_OEN << 16) + (PLD_WBN << 14) + \
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(PLD_WBF << 12) + (PLD_TH << 9) + (PLD_RE << 8) + (PLD_SOR << 7) + (PLD_BEM << 6) + (PLD_PEN << 5))
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/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
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#define PLD_BS 0 /* 1 MByte */
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/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
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#define PLD_BU 3 /* R/W */
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/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
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#define PLD_BW 0 /* 16Bit */
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#define PLD_CR ((PER_PLD_ADDR & 0xfff00000) + (PLD_BS << 17) + (PLD_BU << 15) + (PLD_BW << 13))
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/* timings */
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#define PER_BOARD_ADDR (PER_UART1_ADDR+(1024*1024))
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/* Dummy CS to get the board revision */
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#define BOARD_BME 0 /* Burst disable */
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#define BOARD_TWE 255 /* 255 * 30ns 120ns Waitstates (access=TWT+1+TH) */
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#define BOARD_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
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#define BOARD_OEN 1 /* Cycles from CS low to OE low */
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#define BOARD_WBN 1 /* Cycles from CS low to WE low */
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#define BOARD_WBF 1 /* Cycles from WE high to CS high */
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#define BOARD_TH 2 /* Number of hold cycles after transfer */
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#define BOARD_RE 0 /* Ready disabled */
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#define BOARD_SOR 1 /* Sample on Ready disabled */
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#define BOARD_BEM 0 /* Byte Write only active on Write cycles */
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#define BOARD_PEN 0 /* Parity disable */
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#define BOARD_AP ((BOARD_BME << 31) + (BOARD_TWE << 23) + (BOARD_CSN << 18) + (BOARD_OEN << 16) + (BOARD_WBN << 14) + \
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(BOARD_WBF << 12) + (BOARD_TH << 9) + (BOARD_RE << 8) + (BOARD_SOR << 7) + (BOARD_BEM << 6) + (BOARD_PEN << 5))
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/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
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#define BOARD_BS 0 /* 1 MByte */
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/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
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#define BOARD_BU 3 /* R/W */
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/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
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#define BOARD_BW 0 /* 16Bit */
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#define BOARD_CR ((PER_BOARD_ADDR & 0xfff00000) + (BOARD_BS << 17) + (BOARD_BU << 15) + (BOARD_BW << 13))
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/* UART0 CS2 */
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#define UART0_BME 0 /* Burst disable */
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#define UART0_TWE 7 /* 7 * 30ns 210ns Waitstates (access=TWT+1+TH) */
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#define UART0_CSN 1 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
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#define UART0_OEN 1 /* Cycles from CS low to OE low */
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#define UART0_WBN 1 /* Cycles from CS low to WE low */
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#define UART0_WBF 1 /* Cycles from WE high to CS high */
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#define UART0_TH 2 /* Number of hold cycles after transfer */
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#define UART0_RE 0 /* Ready disabled */
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#define UART0_SOR 1 /* Sample on Ready disabled */
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#define UART0_BEM 0 /* Byte Write only active on Write cycles */
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#define UART0_PEN 0 /* Parity disable */
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#define UART0_AP ((UART0_BME << 31) + (UART0_TWE << 23) + (UART0_CSN << 18) + (UART0_OEN << 16) + (UART0_WBN << 14) + \
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(UART0_WBF << 12) + (UART0_TH << 9) + (UART0_RE << 8) + (UART0_SOR << 7) + (UART0_BEM << 6) + (UART0_PEN << 5))
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/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
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#define UART0_BS 0 /* 1 MByte */
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/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
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#define UART0_BU 3 /* R/W */
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/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
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#define UART0_BW 0 /* 8Bit */
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#define UART0_CR ((PER_UART0_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
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/* UART1 CS3 */
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#define UART1_AP UART0_AP /* same timing as UART0 */
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#define UART1_CR ((PER_UART1_ADDR & 0xfff00000) + (UART0_BS << 17) + (UART0_BU << 15) + (UART0_BW << 13))
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/* Flash CS0 or CS 1 */
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/* 0x7F8FFE80 slowest timing at all... */
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#define FLASH_BME_B 1 /* Burst enable */
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#define FLASH_FWT_B 0x6 /* 6 * 30ns 210ns First Wait Access */
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#define FLASH_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
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#define FLASH_BME 0 /* Burst disable */
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#define FLASH_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
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#define FLASH_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
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#define FLASH_OEN 1 /* Cycles from CS low to OE low */
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#define FLASH_WBN 1 /* Cycles from CS low to WE low */
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#define FLASH_WBF 1 /* Cycles from WE high to CS high */
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#define FLASH_TH 2 /* Number of hold cycles after transfer */
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#define FLASH_RE 0 /* Ready disabled */
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#define FLASH_SOR 1 /* Sample on Ready disabled */
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#define FLASH_BEM 0 /* Byte Write only active on Write cycles */
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#define FLASH_PEN 0 /* Parity disable */
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/* Access Parameter Register for non Boot */
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#define FLASH_AP ((FLASH_BME << 31) + (FLASH_TWE << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
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(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
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/* Access Parameter Register for Boot */
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#define FLASH_AP_B ((FLASH_BME_B << 31) + (FLASH_FWT_B << 26) + (FLASH_BWT_B << 23) + (FLASH_CSN << 18) + (FLASH_OEN << 16) + (FLASH_WBN << 14) + \
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(FLASH_WBF << 12) + (FLASH_TH << 9) + (FLASH_RE << 8) + (FLASH_SOR << 7) + (FLASH_BEM << 6) + (FLASH_PEN << 5))
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/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
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#define FLASH_BS FLASH_SIZE_PRELIM /* 4 MByte */
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/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
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#define FLASH_BU 3 /* R/W */
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/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
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#define FLASH_BW 1 /* 16Bit */
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/* CR register for Boot */
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#define FLASH_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
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/* CR register for non Boot */
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#define FLASH_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (FLASH_BS << 17) + (FLASH_BU << 15) + (FLASH_BW << 13))
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/* MPS CS1 or CS0 */
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/* Boot CS: */
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#define MPS_BME_B 1 /* Burst enable */
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#define MPS_FWT_B 0x6/* 6 * 30ns 210ns First Wait Access */
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#define MPS_BWT_B 0x6 /* 6 * 30ns 210ns Burst Wait Access */
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#define MPS_BME 0 /* Burst disable */
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#define MPS_TWE 0xb/* 11 * 30ns 330ns Waitstates (access=TWT+1+TH) */
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#define MPS_CSN 0 /* Chipselect is driven inactive for 1 Cycle BTW transfers */
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#define MPS_OEN 1 /* Cycles from CS low to OE low */
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#define MPS_WBN 1 /* Cycles from CS low to WE low */
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#define MPS_WBF 1 /* Cycles from WE high to CS high */
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#define MPS_TH 2 /* Number of hold cycles after transfer */
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#define MPS_RE 0 /* Ready disabled */
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#define MPS_SOR 1 /* Sample on Ready disabled */
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#define MPS_BEM 0 /* Byte Write only active on Write cycles */
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#define MPS_PEN 0 /* Parity disable */
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/* Access Parameter Register for non Boot */
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#define MPS_AP ((MPS_BME << 31) + (MPS_TWE << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
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(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
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/* Access Parameter Register for Boot */
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#define MPS_AP_B ((MPS_BME_B << 31) + (MPS_FWT_B << 26) + (MPS_BWT_B << 23) + (MPS_CSN << 18) + (MPS_OEN << 16) + (MPS_WBN << 14) + \
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(MPS_WBF << 12) + (MPS_TH << 9) + (MPS_RE << 8) + (MPS_SOR << 7) + (MPS_BEM << 6) + (MPS_PEN << 5))
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/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */
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#define MPS_BS 2 /* 4 MByte */
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#define MPS_BS_B FLASH_SIZE_PRELIM /* 1 MByte */
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/* Usage: 0=disabled, 1=Read only, 2=Write Only, 3=R/W */
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#define MPS_BU 3 /* R/W */
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/* Bus width: 0=8Bit, 1=16Bit, 2=32Bit, 3=Reserved */
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#define MPS_BW 0 /* 8Bit */
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/* CR register for Boot */
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#define MPS_CR_B ((FLASH_BASE_PRELIM & 0xfff00000) + (MPS_BS_B << 17) + (MPS_BU << 15) + (MPS_BW << 13))
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/* CR register for non Boot */
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#define MPS_CR ((MULTI_PURPOSE_SOCKET_ADDR & 0xfff00000) + (MPS_BS << 17) + (MPS_BU << 15) + (MPS_BW << 13))
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