mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-27 13:33:40 +00:00
682011ff69
- Added support for custom keyboards, initialized by defining a
board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
- Added support for the RBC823 board.
- cpu/mpc8xx/lcd.c now automatically calculates the
Horizontal Pixel Count field.
* Fix alignment problem in BOOTP (dhcp_leasetime option)
[pointed out by Nicolas Lacressonnière, 2 Jun 2003]
* Patch by Mark Rakes, 14 May 2003:
add support for Intel e1000 gig cards.
* Patch by Nye Liu, 3 Jun 2003:
fix critical typo in MAMR definition (include/mpc8xx.h)
* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.
* Patch by Klaus Heydeck, 2 Jun 2003
Minor changes for KUP4K configuration
113 lines
4.6 KiB
C
113 lines
4.6 KiB
C
/*---------------------------------------------------------------------------- */
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/* */
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/* File generated by S1D13706CFG.EXE */
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/* */
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/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */
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/* All rights reserved. */
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/* */
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/*---------------------------------------------------------------------------- */
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/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */
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#define S1D_DISPLAY_WIDTH 320
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#define S1D_DISPLAY_HEIGHT 240
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#define S1D_DISPLAY_BPP 8
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#define S1D_DISPLAY_SCANLINE_BYTES 320
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#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L
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#define S1D_PHYSICAL_VMEM_SIZE 0x14000L
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#define S1D_PHYSICAL_REG_ADDR 0x80080000L
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#define S1D_PHYSICAL_REG_SIZE 0x100
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#define S1D_DISPLAY_PCLK 6250
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#define S1D_PALETTE_SIZE 256
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#define S1D_REGDELAYOFF 0xFFFE
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#define S1D_REGDELAYON 0xFFFF
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#define S1D_WRITE_PALETTE(p,i,r,g,b) \
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{ \
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((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \
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((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \
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((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \
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((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \
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}
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#define S1D_READ_PALETTE(p,i,r,g,b) \
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{ \
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((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \
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r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \
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g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \
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b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \
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}
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typedef unsigned short S1D_INDEX;
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typedef unsigned char S1D_VALUE;
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typedef struct
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{
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S1D_INDEX Index;
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S1D_VALUE Value;
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} S1D_REGS;
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static S1D_REGS aS1DRegs[] =
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{
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{0x04,0x10}, /* BUSCLK MEMCLK Config Register */
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#if 0
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{0x05,0x32}, /* PCLK Config Register */
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#endif
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{0x10,0xD0}, /* PANEL Type Register */
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{0x11,0x00}, /* MOD Rate Register */
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#if 0
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{0x12,0x34}, /* Horizontal Total Register */
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#endif
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{0x14,0x27}, /* Horizontal Display Period Register */
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{0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */
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{0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */
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{0x18,0xF0}, /* Vertical Total Register 0 */
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{0x19,0x00}, /* Vertical Total Register 1 */
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{0x1C,0xEF}, /* Vertical Display Period Register 0 */
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{0x1D,0x00}, /* Vertical Display Period Register 1 */
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{0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */
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{0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */
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{0x20,0x87}, /* Horizontal Sync Pulse Width Register */
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{0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */
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{0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */
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{0x24,0x80}, /* Vertical Sync Pulse Width Register */
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{0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */
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{0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */
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{0x70,0x83}, /* Display Mode Register */
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{0x71,0x00}, /* Special Effects Register */
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{0x74,0x00}, /* Main Window Display Start Address Register 0 */
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{0x75,0x00}, /* Main Window Display Start Address Register 1 */
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{0x76,0x00}, /* Main Window Display Start Address Register 2 */
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{0x78,0x50}, /* Main Window Address Offset Register 0 */
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{0x79,0x00}, /* Main Window Address Offset Register 1 */
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{0x7C,0x00}, /* Sub Window Display Start Address Register 0 */
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{0x7D,0x00}, /* Sub Window Display Start Address Register 1 */
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{0x7E,0x00}, /* Sub Window Display Start Address Register 2 */
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{0x80,0x50}, /* Sub Window Address Offset Register 0 */
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{0x81,0x00}, /* Sub Window Address Offset Register 1 */
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{0x84,0x00}, /* Sub Window X Start Pos Register 0 */
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{0x85,0x00}, /* Sub Window X Start Pos Register 1 */
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{0x88,0x00}, /* Sub Window Y Start Pos Register 0 */
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{0x89,0x00}, /* Sub Window Y Start Pos Register 1 */
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{0x8C,0x4F}, /* Sub Window X End Pos Register 0 */
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{0x8D,0x00}, /* Sub Window X End Pos Register 1 */
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{0x90,0xEF}, /* Sub Window Y End Pos Register 0 */
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{0x91,0x00}, /* Sub Window Y End Pos Register 1 */
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{0xA0,0x00}, /* Power Save Config Register */
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{0xA1,0x00}, /* CPU Access Control Register */
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{0xA2,0x00}, /* Software Reset Register */
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{0xA3,0x00}, /* BIG Endian Support Register */
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{0xA4,0x00}, /* Scratch Pad Register 0 */
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{0xA5,0x00}, /* Scratch Pad Register 1 */
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{0xA8,0x01}, /* GPIO Config Register 0 */
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{0xA9,0x80}, /* GPIO Config Register 1 */
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{0xAC,0x01}, /* GPIO Status Control Register 0 */
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{0xAD,0x00}, /* GPIO Status Control Register 1 */
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{0xB0,0x10}, /* PWM CV Clock Control Register */
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{0xB1,0x80}, /* PWM CV Clock Config Register */
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{0xB2,0x00}, /* CV Clock Burst Length Register */
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{0xB3,0xA0}, /* PWM Clock Duty Cycle Register */
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{0xAD,0x80}, /* reset seq */
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{0x70,0x03}, /* */
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};
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