mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-27 13:33:40 +00:00
8bde7f776c
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
85 lines
1.9 KiB
ArmAsm
85 lines
1.9 KiB
ArmAsm
/*
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* Memory Setup stuff - taken from ???
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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/* some parameters for the board */
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SYSCON2: .long 0x80001100
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MEMCFG1: .long 0x80000180
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MEMCFG2: .long 0x800001C0
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DRFPR: .long 0x80000200
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syscon2_mask: .long 0x00000004
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memcfg1_val: .long 0x160c1414
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memcfg2_mask: .long 0x0000ffff @ only set lower 16 bits
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memcfg2_val: .long 0x00000000 @ upper 16 bits are reserved for CS7 + CS6
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drfpr_val: .long 0x00000081
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/* setting up the memory */
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.globl memsetup
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memsetup:
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/*
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* DRFPR
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* 64kHz DRAM refresh
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*/
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ldr r0, DRFPR
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ldr r1, drfpr_val
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str r1, [r0]
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/*
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* SYSCON2: clear bit 2, DRAM is 32 bits wide
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*/
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ldr r0, SYSCON2
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ldr r2, [r0]
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ldr r1, syscon2_mask
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bic r2, r2, r1
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str r2, [r0]
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/*
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* MEMCFG1
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* Setting up Keyboard at CS3, 8 Bit, 3 Waitstates
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* Setting up CS8900 (Ethernet) at CS2, 32 Bit, 5 Waitstates
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* Setting up flash at CS0 and CS1, 32 Bit, 3 Waitstates
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*/
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ldr r0, MEMCFG1
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ldr r1, memcfg1_val
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str r1, [r0]
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/*
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* MEMCFG2
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* Setting up ? with 0
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*
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*/
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ldr r0, MEMCFG2
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ldr r2, [r0]
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ldr r1, memcfg2_mask
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bic r2, r2, r1
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ldr r1, memcfg2_val
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orr r2, r2, r1
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str r2, [r0]
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/* everything is fine now */
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mov pc, lr
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