mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 09:30:10 +00:00
f8a1b33889
U-boot is intended to replace linux kernel in android boot image(ABL), and it's FIT payload to replace initramfs file. The boot process is similar to boot image with linux: - android bootloader (ABL) unpacks android boot image - ABL sets `linux,initrd-start property` in chosen node in unpacked FDT - ABL sets x0 register to FDT address, and passes control to u-boot - u-boot reads x0 register, and stores it in `prevbl_fdt_addr` env variable - u-boot reads `linux,initrd-start` property, and stores it in `prevbl_initrd_start_addr` In this way, u-boot bootcmd relies on `prevbl_initrd_start_addr` env variable, and boils down to `bootm $prevbl_initrd_start_addr`. If more control on boot process is desired, pack a boot script in FIT image, and put it to default configuration What done: - strip unneeded config options - add FIT image support - add framebuffer node, u-boot logo and video console - increase LMB_MAX_REGIONS, to store all linux dtb reserved memory regions - add linux kernel image header Uart driver causes hang, when u-boot is used in android boot image instead of linux. Temporary disable console driver, until investigated and fixed. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com>
114 lines
2.4 KiB
Text
114 lines
2.4 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Qualcomm SDM845 chip device tree source
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*
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* (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
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*
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*/
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/dts-v1/;
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#include "skeleton64.dtsi"
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/ {
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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gcc: clock-controller@100000 {
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u-boot,dm-pre-reloc;
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compatible = "qcom,gcc-sdm845";
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reg = <0x100000 0x1f0000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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gpio_north: gpio_north@3900000 {
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u-boot,dm-pre-reloc;
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#gpio-cells = <2>;
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compatible = "qcom,sdm845-pinctrl";
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reg = <0x3900000 0x400000>;
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gpio-count = <150>;
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gpio-controller;
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gpio-ranges = <&gpio_north 0 0 150>;
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gpio-bank-name = "soc_north.";
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};
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tlmm_north: pinctrl_north@3900000 {
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u-boot,dm-pre-reloc;
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compatible = "qcom,tlmm-sdm845";
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reg = <0x3900000 0x400000>;
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gpio-count = <150>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm_north 0 0 150>;
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/* DEBUG UART */
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qup_uart9: qup-uart9-default {
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pins = "GPIO_4", "GPIO_5";
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function = "gpio";
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};
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};
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debug_uart: serial@a84000 {
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compatible = "qcom,msm-geni-uart";
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reg = <0xa84000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc 0x58>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_uart9>;
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qcom,wrapper-core = <0x8a>;
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status = "disabled";
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};
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spmi@c440000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0xc440000 0x1100>,
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<0xc600000 0x2000000>,
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<0xe600000 0x100000>;
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reg-names = "cnfg", "core", "obsrvr";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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qcom,revid@100 {
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compatible = "qcom,qpnp-revid";
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reg = <0x100 0x100>;
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};
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pmic0: pm8998@0 {
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compatible = "qcom,spmi-pmic";
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reg = <0x0 0x1>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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pm8998_pon: pm8998_pon@800 {
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compatible = "qcom,pm8998-pwrkey";
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reg = <0x800 0x100>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "pm8998_key.";
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};
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pm8998_gpios: pm8998_gpios@c000 {
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compatible = "qcom,pm8998-gpio";
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reg = <0xc000 0x1a00>;
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gpio-controller;
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gpio-count = <21>;
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#gpio-cells = <2>;
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gpio-bank-name = "pm8998.";
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};
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};
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pmic1: pm8998@1 {
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compatible = "qcom,spmi-pmic";
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reg = <0x1 0x0>;
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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};
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};
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};
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};
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