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51ca6a2583
QSPI1 used the clock of QSPI0, fix it.
Fixes: 5eecc37bb1 ("ARM: dts: at91: sama7g5: Add QSPI0 and OSPI1 nodes")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
893 lines
26 KiB
Text
893 lines
26 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* sama7g5.dtsi - Device Tree Include file for SAMA7G5 family SoC
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*
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* Copyright (C) 2020 Microchip Technology, Inc. and its subsidiaries
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*
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* Author: Eugen Hristev <eugen.hristev@microchip.com>
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* Author: Claudiu Beznea <claudiu.beznea@microchip.com>
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*
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clk/at91.h>
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Microchip SAMA7G5 family SoC";
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compatible = "microchip,sama7g5";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>;
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clock-names = "cpu", "master", "xtal";
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};
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};
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cpu_opp_table: opp-table {
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compatible = "operating-points-v2";
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opp-90000000 {
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opp-hz = /bits/ 64 <90000000>;
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opp-microvolt = <1050000 1050000 1225000>;
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clock-latency-ns = <320000>;
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};
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opp-250000000 {
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opp-hz = /bits/ 64 <250000000>;
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opp-microvolt = <1050000 1050000 1225000>;
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clock-latency-ns = <320000>;
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};
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opp-600000000 {
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opp-hz = /bits/ 64 <600000000>;
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opp-microvolt = <1050000 1050000 1225000>;
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clock-latency-ns = <320000>;
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opp-suspend;
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};
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opp-800000000 {
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opp-hz = /bits/ 64 <800000000>;
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opp-microvolt = <1150000 1125000 1225000>;
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clock-latency-ns = <320000>;
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};
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opp-1000000002 {
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opp-hz = /bits/ 64 <1000000002>;
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opp-microvolt = <1250000 1225000 1300000>;
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clock-latency-ns = <320000>;
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};
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};
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clocks {
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slow_rc_osc: slow_rc_osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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};
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main_rc: main_rc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <12000000>;
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};
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slow_xtal: slow_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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main_xtal: main_xtal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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usb_clk: usb_clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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};
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vddout25: fixed-regulator-vddout25 {
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compatible = "regulator-fixed";
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regulator-name = "VDDOUT25";
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-boot-on;
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status = "disabled";
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};
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ns_sram: sram@100000 {
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compatible = "mmio-sram";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x100000 0x20000>;
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ranges;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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nfc_sram: sram@600000 {
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compatible = "mmio-sram";
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no-memory-wc;
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reg = <0x00600000 0x2400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x00600000 0x2400>;
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};
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nfc_io: nfc-io@10000000 {
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compatible = "atmel,sama5d3-nfc-io", "syscon";
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reg = <0x10000000 0x8000000>;
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};
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ebi: ebi@40000000 {
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compatible = "atmel,sama5d3-ebi";
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#address-cells = <2>;
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#size-cells = <1>;
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atmel,smc = <&hsmc>;
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reg = <0x40000000 0x20000000>;
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ranges = <0x0 0x0 0x40000000 0x8000000
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0x1 0x0 0x48000000 0x8000000
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0x2 0x0 0x50000000 0x8000000
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0x3 0x0 0x58000000 0x8000000>;
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clocks = <&pmc PMC_TYPE_CORE 13>; /* PMC_MCK1 */
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status = "disabled";
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nand_controller: nand-controller {
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compatible = "atmel,sama5d3-nand-controller";
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atmel,nfc-sram = <&nfc_sram>;
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atmel,nfc-io = <&nfc_io>;
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ecc-engine = <&pmecc>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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status = "disabled";
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};
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};
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securam: securam@e0000000 {
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compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram";
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reg = <0xe0000000 0x4000>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xe0000000 0x4000>;
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no-memory-wc;
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};
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secumod: secumod@e0004000 {
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compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon";
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reg = <0xe0004000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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sfrbu: sfr@e0008000 {
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compatible = "microchip,sama7g5-sfrbu", "atmel,sama5d2-sfrbu", "syscon";
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reg = <0xe0008000 0x20>;
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};
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pinctrl: pinctrl@e0014000 {
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compatible = "microchip,sama7g5-gpio";
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reg = <0xe0014000 0x800>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
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pioA: pinctrl_default {
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-controller;
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#gpio-cells = <2>;
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compatible = "microchip,sama7g5-pinctrl";
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};
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};
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pmc: pmc@e0018000 {
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compatible = "microchip,sama7g5-pmc", "syscon";
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reg = <0xe0018000 0x200>;
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interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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#clock-cells = <2>;
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clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>, <&main_rc>;
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clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
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};
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shdwc: shdwc@e001d010 {
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compatible = "microchip,sama7g5-shdwc", "syscon";
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reg = <0xe001d010 0x10>;
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clocks = <&clk32k 0>;
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#address-cells = <1>;
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#size-cells = <0>;
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atmel,wakeup-rtc-timer;
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atmel,wakeup-rtt-timer;
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status = "disabled";
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};
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rtt: rtt@e001d020 {
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compatible = "microchip,sama7g5-rtt", "microchip,sam9x60-rtt", "atmel,at91sam9260-rtt";
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reg = <0xe001d020 0x30>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk32k 0>;
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};
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reset_controller: rstc@e001d000 {
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compatible = "microchip,sama7g5-rstc", "microchip,sam9x60-rstc";
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reg = <0xe001d000 0xc>, <0xe001d0e4 0x4>;
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#reset-cells = <1>;
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clocks = <&clk32k 0>;
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};
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clk32k: clock-controller@e001d050 {
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compatible = "microchip,sama7g5-sckc", "microchip,sam9x60-sckc";
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reg = <0xe001d050 0x4>;
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clocks = <&slow_rc_osc>, <&slow_xtal>;
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#clock-cells = <1>;
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};
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gpbr: gpbr@e001d060 {
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compatible = "microchip,sama7g5-gpbr", "syscon";
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reg = <0xe001d060 0x48>;
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};
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rtc: rtc@e001d0a8 {
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compatible = "microchip,sama7g5-rtc", "microchip,sam9x60-rtc";
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reg = <0xe001d0a8 0x30>;
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk32k 1>;
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};
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ps_wdt: watchdog@e001d180 {
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compatible = "microchip,sama7g5-wdt";
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reg = <0xe001d180 0x24>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk32k 0>;
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};
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chipid@e0020000 {
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compatible = "microchip,sama7g5-chipid";
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reg = <0xe0020000 0x8>;
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};
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tcb1: timer@e0800000 {
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compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xe0800000 0x100>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 91>, <&pmc PMC_TYPE_PERIPHERAL 92>, <&pmc PMC_TYPE_PERIPHERAL 93>, <&clk32k 1>;
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clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
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};
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hsmc: hsmc@e0808000 {
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compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
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reg = <0xe0808000 0x1000>;
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pmecc: ecc-engine@e0808070 {
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compatible = "atmel,sama5d2-pmecc";
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reg = <0xe0808070 0x490>,
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<0xe0808500 0x200>;
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};
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};
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qspi0: spi@e080c000 {
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compatible = "microchip,sama7g5-ospi";
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reg = <0xe080c000 0x400>, <0x20000000 0x10000000>;
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reg-names = "qspi_base", "qspi_mmap";
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(41)>,
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<&dma0 AT91_XDMAC_DT_PERID(40)>;
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dma-names = "tx", "rx";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 78>, <&pmc PMC_TYPE_GCK 78>;
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clock-names = "pclk", "gclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 78>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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qspi1: spi@e0810000 {
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compatible = "microchip,sama7g5-qspi";
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reg = <0xe0810000 0x400>, <0x30000000 0x10000000>;
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reg-names = "qspi_base", "qspi_mmap";
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interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dma0 AT91_XDMAC_DT_PERID(43)>,
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<&dma0 AT91_XDMAC_DT_PERID(42)>;
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dma-names = "tx", "rx";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 79>, <&pmc PMC_TYPE_GCK 79>;
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clock-names = "pclk", "gclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 79>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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can0: can@e0828000 {
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compatible = "bosch,m_can";
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reg = <0xe0828000 0x100>, <0x100000 0x7800>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 61>, <&pmc PMC_TYPE_GCK 61>;
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clock-names = "hclk", "cclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 61>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */
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assigned-clock-rates = <40000000>;
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bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>;
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status = "disabled";
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};
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can1: can@e082c000 {
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compatible = "bosch,m_can";
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reg = <0xe082c000 0x100>, <0x100000 0xbc00>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 62>, <&pmc PMC_TYPE_GCK 62>;
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clock-names = "hclk", "cclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 62>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */
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assigned-clock-rates = <40000000>;
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bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>;
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status = "disabled";
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};
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can2: can@e0830000 {
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compatible = "bosch,m_can";
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reg = <0xe0830000 0x100>, <0x100000 0x10000>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 63>, <&pmc PMC_TYPE_GCK 63>;
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clock-names = "hclk", "cclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 63>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */
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assigned-clock-rates = <40000000>;
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bosch,mram-cfg = <0xbc00 0 0 64 0 0 32 32>;
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status = "disabled";
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};
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can3: can@e0834000 {
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compatible = "bosch,m_can";
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reg = <0xe0834000 0x100>, <0x110000 0x4400>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 64>, <&pmc PMC_TYPE_GCK 64>;
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clock-names = "hclk", "cclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 64>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */
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assigned-clock-rates = <40000000>;
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bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
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status = "disabled";
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};
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can4: can@e0838000 {
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compatible = "bosch,m_can";
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reg = <0xe0838000 0x100>, <0x110000 0x8800>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 65>, <&pmc PMC_TYPE_GCK 65>;
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clock-names = "hclk", "cclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 65>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */
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assigned-clock-rates = <40000000>;
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bosch,mram-cfg = <0x4400 0 0 64 0 0 32 32>;
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status = "disabled";
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};
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can5: can@e083c000 {
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compatible = "bosch,m_can";
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reg = <0xe083c000 0x100>, <0x110000 0xcc00>;
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reg-names = "m_can", "message_ram";
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>;
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clock-names = "hclk", "cclk";
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assigned-clocks = <&pmc PMC_TYPE_GCK 66>;
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assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */
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assigned-clock-rates = <40000000>;
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bosch,mram-cfg = <0x8800 0 0 64 0 0 32 32>;
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status = "disabled";
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};
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adc: adc@e1000000 {
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compatible = "microchip,sama7g5-adc";
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reg = <0xe1000000 0x200>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pmc PMC_TYPE_GCK 26>;
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assigned-clocks = <&pmc PMC_TYPE_GCK 26>;
|
|
assigned-clock-rates = <100000000>;
|
|
clock-names = "adc_clk";
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(0)>;
|
|
dma-names = "rx";
|
|
atmel,min-sample-rate-hz = <200000>;
|
|
atmel,max-sample-rate-hz = <20000000>;
|
|
atmel,startup-time-ms = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdmmc0: mmc@e1204000 {
|
|
compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
|
|
reg = <0xe1204000 0x4000>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
|
|
clock-names = "hclock", "multclk";
|
|
assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
|
|
assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
|
|
assigned-clock-rates = <200000000>;
|
|
microchip,sdcal-inverted;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdmmc1: mmc@e1208000 {
|
|
compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
|
|
reg = <0xe1208000 0x4000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
|
|
clock-names = "hclock", "multclk";
|
|
assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
|
|
assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
|
|
assigned-clock-rates = <200000000>;
|
|
microchip,sdcal-inverted;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdmmc2: mmc@e120c000 {
|
|
compatible = "microchip,sama7g5-sdhci", "microchip,sam9x60-sdhci";
|
|
reg = <0xe120c000 0x4000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 82>, <&pmc PMC_TYPE_GCK 82>;
|
|
clock-names = "hclock", "multclk";
|
|
assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div */
|
|
assigned-clocks = <&pmc PMC_TYPE_GCK 82>;
|
|
assigned-clock-rates = <200000000>;
|
|
microchip,sdcal-inverted;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm: pwm@e1604000 {
|
|
compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm";
|
|
reg = <0xe1604000 0x4000>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
#pwm-cells = <3>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 77>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spdifrx: spdifrx@e1614000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "microchip,sama7g5-spdifrx";
|
|
reg = <0xe1614000 0x4000>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(49)>;
|
|
dma-names = "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 84>, <&pmc PMC_TYPE_GCK 84>;
|
|
clock-names = "pclk", "gclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
spdiftx: spdiftx@e1618000 {
|
|
#sound-dai-cells = <0>;
|
|
compatible = "microchip,sama7g5-spdiftx";
|
|
reg = <0xe1618000 0x4000>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(50)>;
|
|
dma-names = "tx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 85>, <&pmc PMC_TYPE_GCK 85>;
|
|
clock-names = "pclk", "gclk";
|
|
};
|
|
|
|
i2s0: i2s@e161c000 {
|
|
compatible = "microchip,sama7g5-i2smcc";
|
|
#sound-dai-cells = <0>;
|
|
reg = <0xe161c000 0x4000>;
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(34)>, <&dma0 AT91_XDMAC_DT_PERID(33)>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
|
|
clock-names = "pclk", "gclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2s1: i2s@e1620000 {
|
|
compatible = "microchip,sama7g5-i2smcc";
|
|
#sound-dai-cells = <0>;
|
|
reg = <0xe1620000 0x4000>;
|
|
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(36)>, <&dma0 AT91_XDMAC_DT_PERID(35)>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>;
|
|
clock-names = "pclk", "gclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
eic: interrupt-controller@e1628000 {
|
|
compatible = "microchip,sama7g5-eic";
|
|
reg = <0xe1628000 0xec>;
|
|
interrupt-parent = <&gic>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
|
|
clock-names = "pclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
pit64b0: timer@e1800000 {
|
|
compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
|
|
reg = <0xe1800000 0x4000>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
|
|
clock-names = "pclk", "gclk";
|
|
};
|
|
|
|
pit64b1: timer@e1804000 {
|
|
compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
|
|
reg = <0xe1804000 0x4000>;
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 71>, <&pmc PMC_TYPE_GCK 71>;
|
|
clock-names = "pclk", "gclk";
|
|
};
|
|
|
|
aes: crypto@e1810000 {
|
|
compatible = "atmel,at91sam9g46-aes";
|
|
reg = <0xe1810000 0x100>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
|
|
clock-names = "aes_clk";
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(2)>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
sha: crypto@e1814000 {
|
|
compatible = "atmel,at91sam9g46-sha";
|
|
reg = <0xe1814000 0x100>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
|
|
clock-names = "sha_clk";
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
|
|
dma-names = "tx";
|
|
};
|
|
|
|
flx0: flexcom@e1818000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xe1818000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xe1818000 0x800>;
|
|
status = "disabled";
|
|
|
|
uart0: serial@200 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0x200 0x200>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
|
|
clock-names = "usart";
|
|
dmas = <&dma1 AT91_XDMAC_DT_PERID(6)>,
|
|
<&dma1 AT91_XDMAC_DT_PERID(5)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,use-dma-rx;
|
|
atmel,use-dma-tx;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx1: flexcom@e181c000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xe181c000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xe181c000 0x800>;
|
|
status = "disabled";
|
|
|
|
i2c1: i2c@600 {
|
|
compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
|
|
reg = <0x600 0x200>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
|
|
atmel,fifo-size = <32>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(7)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(8)>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx3: flexcom@e1824000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xe1824000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xe1824000 0x800>;
|
|
status = "disabled";
|
|
|
|
uart3: serial@200 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0x200 0x200>;
|
|
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
|
|
clock-names = "usart";
|
|
dmas = <&dma1 AT91_XDMAC_DT_PERID(12)>,
|
|
<&dma1 AT91_XDMAC_DT_PERID(11)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,use-dma-rx;
|
|
atmel,use-dma-tx;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
trng: rng@e2010000 {
|
|
compatible = "microchip,sama7g5-trng", "atmel,at91sam9g45-trng";
|
|
reg = <0xe2010000 0x100>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 97>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tdes: crypto@e2014000 {
|
|
compatible = "atmel,at91sam9g46-tdes";
|
|
reg = <0xe2014000 0x100>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 96>;
|
|
clock-names = "tdes_clk";
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(53)>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
flx4: flexcom@e2018000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xe2018000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xe2018000 0x800>;
|
|
status = "disabled";
|
|
|
|
uart4: serial@200 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0x200 0x200>;
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 42>;
|
|
clock-names = "usart";
|
|
dmas = <&dma1 AT91_XDMAC_DT_PERID(14)>,
|
|
<&dma1 AT91_XDMAC_DT_PERID(13)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,use-dma-rx;
|
|
atmel,use-dma-tx;
|
|
atmel,fifo-size = <16>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx7: flexcom@e2024000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xe2024000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xe2024000 0x800>;
|
|
status = "disabled";
|
|
|
|
uart7: serial@200 {
|
|
compatible = "atmel,at91sam9260-usart";
|
|
reg = <0x200 0x200>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
|
|
clock-names = "usart";
|
|
dmas = <&dma1 AT91_XDMAC_DT_PERID(20)>,
|
|
<&dma1 AT91_XDMAC_DT_PERID(19)>;
|
|
dma-names = "tx", "rx";
|
|
atmel,use-dma-rx;
|
|
atmel,use-dma-tx;
|
|
atmel,fifo-size = <16>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
gmac0: ethernet@e2800000 {
|
|
compatible = "cdns,sama7g5-gem";
|
|
reg = <0xe2800000 0x1000>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>, <&pmc PMC_TYPE_GCK 53>;
|
|
clock-names = "pclk", "hclk", "tx_clk", "tsu_clk";
|
|
assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
|
|
assigned-clock-parents = <&pmc PMC_TYPE_CORE 21>; /* eth pll div. */
|
|
assigned-clock-rates = <125000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gmac1: ethernet@e2804000 {
|
|
compatible = "cdns,sama7g5-emac";
|
|
reg = <0xe2804000 0x1000>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
|
|
clock-names = "pclk", "hclk";
|
|
status = "disabled";
|
|
};
|
|
|
|
dma0: dma-controller@e2808000 {
|
|
compatible = "microchip,sama7g5-dma";
|
|
reg = <0xe2808000 0x1000>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
|
|
clock-names = "dma_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
dma1: dma-controller@e280c000 {
|
|
compatible = "microchip,sama7g5-dma";
|
|
reg = <0xe280c000 0x1000>;
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
|
|
clock-names = "dma_clk";
|
|
status = "disabled";
|
|
};
|
|
|
|
/* Place dma2 here despite it's address */
|
|
dma2: dma-controller@e1200000 {
|
|
compatible = "microchip,sama7g5-dma";
|
|
reg = <0xe1200000 0x1000>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
#dma-cells = <1>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
|
|
clock-names = "dma_clk";
|
|
dma-requests = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tcb0: timer@e2814000 {
|
|
compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0xe2814000 0x100>;
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 88>, <&pmc PMC_TYPE_PERIPHERAL 89>, <&pmc PMC_TYPE_PERIPHERAL 90>, <&clk32k 1>;
|
|
clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
|
|
};
|
|
|
|
flx8: flexcom@e2818000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xe2818000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xe2818000 0x800>;
|
|
status = "disabled";
|
|
|
|
i2c8: i2c@600 {
|
|
compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
|
|
reg = <0x600 0x200>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
|
|
atmel,fifo-size = <32>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(21)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(22)>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx9: flexcom@e281c000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xe281c000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xe281c000 0x800>;
|
|
status = "disabled";
|
|
|
|
i2c9: i2c@600 {
|
|
compatible = "microchip,sama7g5-i2c", "microchip,sam9x60-i2c";
|
|
reg = <0x600 0x200>;
|
|
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
|
|
atmel,fifo-size = <32>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(23)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(24)>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
flx11: flexcom@e2824000 {
|
|
compatible = "atmel,sama5d2-flexcom";
|
|
reg = <0xe2824000 0x200>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0xe2824000 0x800>;
|
|
status = "disabled";
|
|
|
|
spi11: spi@400 {
|
|
compatible = "atmel,at91rm9200-spi";
|
|
reg = <0x400 0x200>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&pmc PMC_TYPE_PERIPHERAL 49>;
|
|
clock-names = "spi_clk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
atmel,fifo-size = <32>;
|
|
dmas = <&dma0 AT91_XDMAC_DT_PERID(27)>,
|
|
<&dma0 AT91_XDMAC_DT_PERID(28)>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
uddrc: uddrc@e3800000 {
|
|
compatible = "microchip,sama7g5-uddrc";
|
|
reg = <0xe3800000 0x4000>;
|
|
};
|
|
|
|
ddr3phy: ddr3phy@e3804000 {
|
|
compatible = "microchip,sama7g5-ddr3phy";
|
|
reg = <0xe3804000 0x1000>;
|
|
};
|
|
|
|
gic: interrupt-controller@e8c11000 {
|
|
compatible = "arm,cortex-a7-gic";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
interrupt-parent;
|
|
reg = <0xe8c11000 0x1000>,
|
|
<0xe8c12000 0x2000>;
|
|
};
|
|
};
|
|
};
|