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c39f44dc6f
Move fsl_ddr_get_spd into common mpc8xxx/ddr/main.c as most boards pretty much do the same thing. The only variations are in how many controllers or DIMMs per controller exist. To make this work we standardize on the names of the SPD_EEPROM_ADDRESS defines based on the use case of the board. We allow boards to override get_spd to either do board specific fixups to the SPD data or deal with any unique behavior of how the SPD eeproms are wired up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
255 lines
6.7 KiB
C
255 lines
6.7 KiB
C
/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <hwconfig.h>
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#include <asm/mmu.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include <asm/fsl_law.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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extern fixed_ddr_parm_t fixed_ddr_parm_0[];
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#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
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extern fixed_ddr_parm_t fixed_ddr_parm_1[];
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#endif
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phys_size_t fixed_sdram(void)
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{
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int i;
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char buf[32];
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fsl_ddr_cfg_regs_t ddr_cfg_regs;
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phys_size_t ddr_size;
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unsigned int lawbar1_target_id;
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ulong ddr_freq, ddr_freq_mhz;
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ddr_freq = get_ddr_freq(0);
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ddr_freq_mhz = ddr_freq / 1000000;
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printf("Configuring DDR for %s MT/s data rate\n",
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strmhz(buf, ddr_freq));
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for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
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if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
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(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
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memcpy(&ddr_cfg_regs,
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fixed_ddr_parm_0[i].ddr_settings,
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sizeof(ddr_cfg_regs));
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break;
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}
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}
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if (fixed_ddr_parm_0[i].max_freq == 0)
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panic("Unsupported DDR data rate %s MT/s data rate\n",
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strmhz(buf, ddr_freq));
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ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
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#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
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memcpy(&ddr_cfg_regs,
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fixed_ddr_parm_1[i].ddr_settings,
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sizeof(ddr_cfg_regs));
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ddr_cfg_regs.ddr_cdr1 = DDR_CDR1_DHC_EN;
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 1);
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#endif
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/*
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* setup laws for DDR. If not interleaving, presuming half memory on
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* DDR1 and the other half on DDR2
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*/
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if (fixed_ddr_parm_0[i].ddr_settings->cs[0].config & 0x20000000) {
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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ddr_size,
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LAW_TRGT_IF_DDR_INTRLV) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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}
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} else {
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#if (CONFIG_NUM_DDR_CONTROLLERS == 2)
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/* We require both controllers have identical DIMMs */
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lawbar1_target_id = LAW_TRGT_IF_DDR_1;
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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ddr_size / 2,
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lawbar1_target_id) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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}
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lawbar1_target_id = LAW_TRGT_IF_DDR_2;
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE + ddr_size / 2,
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ddr_size / 2,
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lawbar1_target_id) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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}
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#else
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lawbar1_target_id = LAW_TRGT_IF_DDR_1;
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
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ddr_size,
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lawbar1_target_id) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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}
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#endif
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}
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return ddr_size;
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}
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typedef struct {
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u32 datarate_mhz_low;
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u32 datarate_mhz_high;
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u32 n_ranks;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 cpo;
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u32 write_data_delay;
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u32 force_2T;
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} board_specific_parameters_t;
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/* ranges for parameters:
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* wr_data_delay = 0-6
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* clk adjust = 0-8
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* cpo 2-0x1E (30)
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*/
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/* XXX: these values need to be checked for all interleaving modes. */
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/* XXX: No reliable dual-rank 800 MHz setting has been found. It may
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* seem reliable, but errors will appear when memory intensive
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* program is run. */
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/* XXX: Single rank at 800 MHz is OK. */
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const board_specific_parameters_t board_specific_parameters[][30] = {
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{
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/*
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* memory controller 0
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* lo| hi| num| clk| wrlvl | cpo |wrdata|2T
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* mhz| mhz|ranks|adjst| start | delay|
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*/
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{ 0, 850, 4, 4, 6, 0xff, 2, 0},
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{851, 950, 4, 5, 7, 0xff, 2, 0},
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{951, 1050, 4, 5, 8, 0xff, 2, 0},
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{1051, 1250, 4, 5, 10, 0xff, 2, 0},
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{1251, 1350, 4, 5, 11, 0xff, 2, 0},
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{ 0, 850, 2, 5, 6, 0xff, 2, 0},
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{851, 950, 2, 5, 7, 0xff, 2, 0},
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{951, 1050, 2, 5, 7, 0xff, 2, 0},
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{1051, 1250, 2, 4, 6, 0xff, 2, 0},
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{1251, 1350, 2, 5, 7, 0xff, 2, 0},
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},
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{
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/*
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* memory controller 1
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* lo| hi| num| clk| wrlvl | cpo |wrdata|2T
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* mhz| mhz|ranks|adjst| start | delay|
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*/
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{ 0, 850, 4, 4, 6, 0xff, 2, 0},
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{851, 950, 4, 5, 7, 0xff, 2, 0},
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{951, 1050, 4, 5, 8, 0xff, 2, 0},
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{1051, 1250, 4, 5, 10, 0xff, 2, 0},
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{1251, 1350, 4, 5, 11, 0xff, 2, 0},
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{ 0, 850, 2, 5, 6, 0xff, 2, 0},
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{851, 950, 2, 5, 7, 0xff, 2, 0},
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{951, 1050, 2, 5, 7, 0xff, 2, 0},
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{1051, 1250, 2, 4, 6, 0xff, 2, 0},
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{1251, 1350, 2, 5, 7, 0xff, 2, 0},
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}
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const board_specific_parameters_t *pbsp =
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&(board_specific_parameters[ctrl_num][0]);
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u32 num_params = sizeof(board_specific_parameters[ctrl_num]) /
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sizeof(board_specific_parameters[0][0]);
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u32 i;
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ulong ddr_freq;
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/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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for (i = 0; i < num_params; i++) {
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if (ddr_freq >= pbsp->datarate_mhz_low &&
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ddr_freq <= pbsp->datarate_mhz_high &&
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pdimm[0].n_ranks == pbsp->n_ranks) {
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay = pbsp->write_data_delay;
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popts->clk_adjust = pbsp->clk_adjust;
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popts->wrlvl_start = pbsp->wrlvl_start;
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popts->twoT_en = pbsp->force_2T;
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}
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pbsp++;
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}
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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/*
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* Write leveling override
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*/
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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/*
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* Rtt and Rtt_WR override
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*/
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popts->rtt_override = 0;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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/* DHC_EN =1, ODT = 60 Ohm */
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
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/* override SPD values. rcw_2 should vary at differnt speed */
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if (pdimm[0].n_ranks == 4) {
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popts->rcw_override = 1;
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popts->rcw_1 = 0x000a5a00;
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if (ddr_freq <= 800)
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popts->rcw_2 = 0x00000000;
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else if (ddr_freq <= 1066)
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popts->rcw_2 = 0x00100000;
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else if (ddr_freq <= 1333)
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popts->rcw_2 = 0x00200000;
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else
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popts->rcw_2 = 0x00300000;
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}
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size;
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puts("Initializing....");
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if (fsl_use_spd()) {
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puts("using SPD\n");
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dram_size = fsl_ddr_sdram();
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} else {
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puts("using fixed parameters\n");
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dram_size = fixed_sdram();
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}
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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return dram_size;
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}
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