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ae3527f088
We add RISC-V semihosting based serial console for JTAG based early debugging. The RISC-V semihosting specification is available at: https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc Signed-off-by: Anup Patel <apatel@ventanamicro.com> Signed-off-by: Kautuk Consul <kconsul@ventanamicro.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
24 lines
448 B
C
24 lines
448 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Ventana Micro Systems Inc.
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*/
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#include <common.h>
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long smh_trap(int sysnum, void *addr)
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{
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register int ret asm ("a0") = sysnum;
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register void *param0 asm ("a1") = addr;
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asm volatile (".align 4\n"
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".option push\n"
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".option norvc\n"
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"slli zero, zero, 0x1f\n"
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"ebreak\n"
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"srai zero, zero, 7\n"
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".option pop\n"
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: "+r" (ret) : "r" (param0) : "memory");
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return ret;
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}
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