mirror of
https://github.com/AsahiLinux/u-boot
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d928664f41
All the 74xx_7xx boards are still non-generic boards: P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2 Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefan Roese <sr@denx.de> Acked-by: York Sun <yorksun@freescale.com> Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Nye Liu <nyet@zumanetworks.com> Cc: Roy Zang <tie-fei.zang@freescale.com>
816 lines
19 KiB
C
816 lines
19 KiB
C
/*
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* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Andreas Heppel <aheppel@sysgo.de>
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*
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* (C) Copyright 2002, 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* PCI routines
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <pci.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define PCI_HOSE_OP(rw, size, type) \
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int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
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pci_dev_t dev, \
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int offset, type value) \
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{ \
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return hose->rw##_##size(hose, dev, offset, value); \
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}
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PCI_HOSE_OP(read, byte, u8 *)
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PCI_HOSE_OP(read, word, u16 *)
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PCI_HOSE_OP(read, dword, u32 *)
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PCI_HOSE_OP(write, byte, u8)
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PCI_HOSE_OP(write, word, u16)
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PCI_HOSE_OP(write, dword, u32)
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#define PCI_OP(rw, size, type, error_code) \
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int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
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{ \
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struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
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\
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if (!hose) \
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{ \
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error_code; \
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return -1; \
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} \
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\
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return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
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}
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PCI_OP(read, byte, u8 *, *value = 0xff)
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PCI_OP(read, word, u16 *, *value = 0xffff)
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PCI_OP(read, dword, u32 *, *value = 0xffffffff)
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PCI_OP(write, byte, u8, )
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PCI_OP(write, word, u16, )
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PCI_OP(write, dword, u32, )
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#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
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int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
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pci_dev_t dev, \
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int offset, type val) \
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{ \
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u32 val32; \
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\
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if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
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*val = -1; \
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return -1; \
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} \
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\
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*val = (val32 >> ((offset & (int)off_mask) * 8)); \
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\
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return 0; \
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}
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#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
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int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
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pci_dev_t dev, \
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int offset, type val) \
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{ \
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u32 val32, mask, ldata, shift; \
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\
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if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
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return -1; \
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\
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shift = ((offset & (int)off_mask) * 8); \
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ldata = (((unsigned long)val) & val_mask) << shift; \
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mask = val_mask << shift; \
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val32 = (val32 & ~mask) | ldata; \
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\
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if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
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return -1; \
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\
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return 0; \
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}
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PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
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PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
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PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
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PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
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/* Get a virtual address associated with a BAR region */
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void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
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{
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pci_addr_t pci_bus_addr;
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u32 bar_response;
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/* read BAR address */
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pci_read_config_dword(pdev, bar, &bar_response);
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pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
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/*
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* Pass "0" as the length argument to pci_bus_to_virt. The arg
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* isn't actualy used on any platform because u-boot assumes a static
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* linear mapping. In the future, this could read the BAR size
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* and pass that as the size if needed.
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*/
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return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
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}
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/*
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*
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*/
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static struct pci_controller* hose_head;
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struct pci_controller *pci_get_hose_head(void)
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{
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if (gd->hose)
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return gd->hose;
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return hose_head;
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}
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void pci_register_hose(struct pci_controller* hose)
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{
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struct pci_controller **phose = &hose_head;
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while(*phose)
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phose = &(*phose)->next;
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hose->next = NULL;
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*phose = hose;
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}
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struct pci_controller *pci_bus_to_hose(int bus)
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{
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struct pci_controller *hose;
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for (hose = pci_get_hose_head(); hose; hose = hose->next) {
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if (bus >= hose->first_busno && bus <= hose->last_busno)
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return hose;
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}
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printf("pci_bus_to_hose() failed\n");
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return NULL;
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}
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struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
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{
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struct pci_controller *hose;
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for (hose = pci_get_hose_head(); hose; hose = hose->next) {
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if (hose->cfg_addr == cfg_addr)
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return hose;
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}
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return NULL;
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}
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int pci_last_busno(void)
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{
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struct pci_controller *hose = pci_get_hose_head();
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if (!hose)
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return -1;
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while (hose->next)
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hose = hose->next;
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return hose->last_busno;
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}
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pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
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{
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struct pci_controller * hose;
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u16 vendor, device;
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u8 header_type;
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pci_dev_t bdf;
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int i, bus, found_multi = 0;
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for (hose = pci_get_hose_head(); hose; hose = hose->next) {
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#ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
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for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
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#else
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for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
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#endif
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for (bdf = PCI_BDF(bus, 0, 0);
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bdf < PCI_BDF(bus + 1, 0, 0);
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bdf += PCI_BDF(0, 0, 1)) {
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if (pci_skip_dev(hose, bdf))
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continue;
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if (!PCI_FUNC(bdf)) {
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pci_read_config_byte(bdf,
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PCI_HEADER_TYPE,
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&header_type);
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found_multi = header_type & 0x80;
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} else {
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if (!found_multi)
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continue;
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}
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pci_read_config_word(bdf,
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PCI_VENDOR_ID,
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&vendor);
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pci_read_config_word(bdf,
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PCI_DEVICE_ID,
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&device);
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for (i = 0; ids[i].vendor != 0; i++) {
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if (vendor == ids[i].vendor &&
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device == ids[i].device) {
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if (index <= 0)
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return bdf;
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index--;
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}
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}
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}
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}
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return -1;
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}
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pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
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{
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struct pci_device_id ids[2] = { {}, {0, 0} };
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ids[0].vendor = vendor;
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ids[0].device = device;
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return pci_find_devices(ids, index);
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}
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/*
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*
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*/
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int __pci_hose_phys_to_bus(struct pci_controller *hose,
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phys_addr_t phys_addr,
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unsigned long flags,
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unsigned long skip_mask,
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pci_addr_t *ba)
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{
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struct pci_region *res;
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pci_addr_t bus_addr;
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int i;
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for (i = 0; i < hose->region_count; i++) {
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res = &hose->regions[i];
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if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
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continue;
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if (res->flags & skip_mask)
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continue;
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bus_addr = phys_addr - res->phys_start + res->bus_start;
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if (bus_addr >= res->bus_start &&
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bus_addr < res->bus_start + res->size) {
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*ba = bus_addr;
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return 0;
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}
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}
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return 1;
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}
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pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
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phys_addr_t phys_addr,
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unsigned long flags)
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{
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pci_addr_t bus_addr = 0;
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int ret;
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if (!hose) {
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puts("pci_hose_phys_to_bus: invalid hose\n");
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return bus_addr;
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}
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/*
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* if PCI_REGION_MEM is set we do a two pass search with preference
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* on matches that don't have PCI_REGION_SYS_MEMORY set
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*/
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if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
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ret = __pci_hose_phys_to_bus(hose, phys_addr,
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flags, PCI_REGION_SYS_MEMORY, &bus_addr);
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if (!ret)
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return bus_addr;
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}
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ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
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if (ret)
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puts("pci_hose_phys_to_bus: invalid physical address\n");
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return bus_addr;
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}
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int __pci_hose_bus_to_phys(struct pci_controller *hose,
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pci_addr_t bus_addr,
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unsigned long flags,
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unsigned long skip_mask,
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phys_addr_t *pa)
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{
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struct pci_region *res;
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int i;
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for (i = 0; i < hose->region_count; i++) {
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res = &hose->regions[i];
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if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
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continue;
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if (res->flags & skip_mask)
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continue;
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if (bus_addr >= res->bus_start &&
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(bus_addr - res->bus_start) < res->size) {
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*pa = (bus_addr - res->bus_start + res->phys_start);
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return 0;
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}
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}
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return 1;
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}
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phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
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pci_addr_t bus_addr,
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unsigned long flags)
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{
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phys_addr_t phys_addr = 0;
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int ret;
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if (!hose) {
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puts("pci_hose_bus_to_phys: invalid hose\n");
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return phys_addr;
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}
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/*
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* if PCI_REGION_MEM is set we do a two pass search with preference
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* on matches that don't have PCI_REGION_SYS_MEMORY set
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*/
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if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
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ret = __pci_hose_bus_to_phys(hose, bus_addr,
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flags, PCI_REGION_SYS_MEMORY, &phys_addr);
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if (!ret)
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return phys_addr;
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}
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ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
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if (ret)
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puts("pci_hose_bus_to_phys: invalid physical address\n");
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return phys_addr;
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}
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void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
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u32 addr_and_ctrl)
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{
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int bar;
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bar = PCI_BASE_ADDRESS_0 + barnum * 4;
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pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
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}
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u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
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{
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u32 addr;
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int bar;
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bar = PCI_BASE_ADDRESS_0 + barnum * 4;
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pci_hose_read_config_dword(hose, dev, bar, &addr);
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if (addr & PCI_BASE_ADDRESS_SPACE_IO)
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return addr & PCI_BASE_ADDRESS_IO_MASK;
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else
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return addr & PCI_BASE_ADDRESS_MEM_MASK;
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}
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int pci_hose_config_device(struct pci_controller *hose,
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pci_dev_t dev,
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unsigned long io,
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pci_addr_t mem,
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unsigned long command)
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{
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u32 bar_response;
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unsigned int old_command;
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pci_addr_t bar_value;
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pci_size_t bar_size;
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unsigned char pin;
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int bar, found_mem64;
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debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
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(u64)mem, command);
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pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
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for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
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pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
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pci_hose_read_config_dword(hose, dev, bar, &bar_response);
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if (!bar_response)
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continue;
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found_mem64 = 0;
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/* Check the BAR type and set our address mask */
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if (bar_response & PCI_BASE_ADDRESS_SPACE) {
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bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
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/* round up region base address to a multiple of size */
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io = ((io - 1) | (bar_size - 1)) + 1;
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bar_value = io;
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/* compute new region base address */
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io = io + bar_size;
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} else {
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if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
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PCI_BASE_ADDRESS_MEM_TYPE_64) {
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u32 bar_response_upper;
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u64 bar64;
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pci_hose_write_config_dword(hose, dev, bar + 4,
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0xffffffff);
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pci_hose_read_config_dword(hose, dev, bar + 4,
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&bar_response_upper);
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bar64 = ((u64)bar_response_upper << 32) | bar_response;
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bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
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found_mem64 = 1;
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} else {
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bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
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}
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/* round up region base address to multiple of size */
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mem = ((mem - 1) | (bar_size - 1)) + 1;
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bar_value = mem;
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/* compute new region base address */
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mem = mem + bar_size;
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}
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/* Write it out and update our limit */
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pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
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if (found_mem64) {
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bar += 4;
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#ifdef CONFIG_SYS_PCI_64BIT
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pci_hose_write_config_dword(hose, dev, bar,
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(u32)(bar_value >> 32));
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#else
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pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
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#endif
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}
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}
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/* Configure Cache Line Size Register */
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pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
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/* Configure Latency Timer */
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pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
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/* Disable interrupt line, if device says it wants to use interrupts */
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pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
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if (pin != 0) {
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
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}
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pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
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pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
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(old_command & 0xffff0000) | command);
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return 0;
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}
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/*
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*
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*/
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struct pci_config_table *pci_find_config(struct pci_controller *hose,
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unsigned short class,
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unsigned int vendor,
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unsigned int device,
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unsigned int bus,
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unsigned int dev,
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unsigned int func)
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{
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struct pci_config_table *table;
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for (table = hose->config_table; table && table->vendor; table++) {
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if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
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(table->device == PCI_ANY_ID || table->device == device) &&
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(table->class == PCI_ANY_ID || table->class == class) &&
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(table->bus == PCI_ANY_ID || table->bus == bus) &&
|
|
(table->dev == PCI_ANY_ID || table->dev == dev) &&
|
|
(table->func == PCI_ANY_ID || table->func == func)) {
|
|
return table;
|
|
}
|
|
}
|
|
|
|
return NULL;
|
|
}
|
|
|
|
void pci_cfgfunc_config_device(struct pci_controller *hose,
|
|
pci_dev_t dev,
|
|
struct pci_config_table *entry)
|
|
{
|
|
pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
|
|
entry->priv[2]);
|
|
}
|
|
|
|
void pci_cfgfunc_do_nothing(struct pci_controller *hose,
|
|
pci_dev_t dev, struct pci_config_table *entry)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* HJF: Changed this to return int. I think this is required
|
|
* to get the correct result when scanning bridges
|
|
*/
|
|
extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
|
|
|
|
#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
|
|
const char * pci_class_str(u8 class)
|
|
{
|
|
switch (class) {
|
|
case PCI_CLASS_NOT_DEFINED:
|
|
return "Build before PCI Rev2.0";
|
|
break;
|
|
case PCI_BASE_CLASS_STORAGE:
|
|
return "Mass storage controller";
|
|
break;
|
|
case PCI_BASE_CLASS_NETWORK:
|
|
return "Network controller";
|
|
break;
|
|
case PCI_BASE_CLASS_DISPLAY:
|
|
return "Display controller";
|
|
break;
|
|
case PCI_BASE_CLASS_MULTIMEDIA:
|
|
return "Multimedia device";
|
|
break;
|
|
case PCI_BASE_CLASS_MEMORY:
|
|
return "Memory controller";
|
|
break;
|
|
case PCI_BASE_CLASS_BRIDGE:
|
|
return "Bridge device";
|
|
break;
|
|
case PCI_BASE_CLASS_COMMUNICATION:
|
|
return "Simple comm. controller";
|
|
break;
|
|
case PCI_BASE_CLASS_SYSTEM:
|
|
return "Base system peripheral";
|
|
break;
|
|
case PCI_BASE_CLASS_INPUT:
|
|
return "Input device";
|
|
break;
|
|
case PCI_BASE_CLASS_DOCKING:
|
|
return "Docking station";
|
|
break;
|
|
case PCI_BASE_CLASS_PROCESSOR:
|
|
return "Processor";
|
|
break;
|
|
case PCI_BASE_CLASS_SERIAL:
|
|
return "Serial bus controller";
|
|
break;
|
|
case PCI_BASE_CLASS_INTELLIGENT:
|
|
return "Intelligent controller";
|
|
break;
|
|
case PCI_BASE_CLASS_SATELLITE:
|
|
return "Satellite controller";
|
|
break;
|
|
case PCI_BASE_CLASS_CRYPT:
|
|
return "Cryptographic device";
|
|
break;
|
|
case PCI_BASE_CLASS_SIGNAL_PROCESSING:
|
|
return "DSP";
|
|
break;
|
|
case PCI_CLASS_OTHERS:
|
|
return "Does not fit any class";
|
|
break;
|
|
default:
|
|
return "???";
|
|
break;
|
|
};
|
|
}
|
|
#endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
|
|
|
|
__weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
|
|
{
|
|
/*
|
|
* Check if pci device should be skipped in configuration
|
|
*/
|
|
if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
|
|
#if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
|
|
/*
|
|
* Only skip configuration if "pciconfighost" is not set
|
|
*/
|
|
if (getenv("pciconfighost") == NULL)
|
|
return 1;
|
|
#else
|
|
return 1;
|
|
#endif
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PCI_SCAN_SHOW
|
|
__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
|
|
{
|
|
if (dev == PCI_BDF(hose->first_busno, 0, 0))
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
#endif /* CONFIG_PCI_SCAN_SHOW */
|
|
|
|
int pci_hose_scan_bus(struct pci_controller *hose, int bus)
|
|
{
|
|
unsigned int sub_bus, found_multi = 0;
|
|
unsigned short vendor, device, class;
|
|
unsigned char header_type;
|
|
#ifndef CONFIG_PCI_PNP
|
|
struct pci_config_table *cfg;
|
|
#endif
|
|
pci_dev_t dev;
|
|
#ifdef CONFIG_PCI_SCAN_SHOW
|
|
static int indent = 0;
|
|
#endif
|
|
|
|
sub_bus = bus;
|
|
|
|
for (dev = PCI_BDF(bus,0,0);
|
|
dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
|
|
PCI_MAX_PCI_FUNCTIONS - 1);
|
|
dev += PCI_BDF(0, 0, 1)) {
|
|
|
|
if (pci_skip_dev(hose, dev))
|
|
continue;
|
|
|
|
if (PCI_FUNC(dev) && !found_multi)
|
|
continue;
|
|
|
|
pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
|
|
|
|
pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
|
|
|
|
if (vendor == 0xffff || vendor == 0x0000)
|
|
continue;
|
|
|
|
if (!PCI_FUNC(dev))
|
|
found_multi = header_type & 0x80;
|
|
|
|
debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
|
|
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
|
|
|
|
pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
|
|
pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
|
|
|
|
#ifdef CONFIG_PCI_FIXUP_DEV
|
|
board_pci_fixup_dev(hose, dev, vendor, device, class);
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCI_SCAN_SHOW
|
|
indent++;
|
|
|
|
/* Print leading space, including bus indentation */
|
|
printf("%*c", indent + 1, ' ');
|
|
|
|
if (pci_print_dev(hose, dev)) {
|
|
printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
|
|
PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
|
|
vendor, device, pci_class_str(class >> 8));
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCI_PNP
|
|
sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
|
|
sub_bus);
|
|
#else
|
|
cfg = pci_find_config(hose, class, vendor, device,
|
|
PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
|
|
if (cfg) {
|
|
cfg->config_device(hose, dev, cfg);
|
|
sub_bus = max(sub_bus,
|
|
(unsigned int)hose->current_busno);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PCI_SCAN_SHOW
|
|
indent--;
|
|
#endif
|
|
|
|
if (hose->fixup_irq)
|
|
hose->fixup_irq(hose, dev);
|
|
}
|
|
|
|
return sub_bus;
|
|
}
|
|
|
|
int pci_hose_scan(struct pci_controller *hose)
|
|
{
|
|
#if defined(CONFIG_PCI_BOOTDELAY)
|
|
char *s;
|
|
int i;
|
|
|
|
if (!gd->pcidelay_done) {
|
|
/* wait "pcidelay" ms (if defined)... */
|
|
s = getenv("pcidelay");
|
|
if (s) {
|
|
int val = simple_strtoul(s, NULL, 10);
|
|
for (i = 0; i < val; i++)
|
|
udelay(1000);
|
|
}
|
|
gd->pcidelay_done = 1;
|
|
}
|
|
#endif /* CONFIG_PCI_BOOTDELAY */
|
|
|
|
/*
|
|
* Start scan at current_busno.
|
|
* PCIe will start scan at first_busno+1.
|
|
*/
|
|
/* For legacy support, ensure current >= first */
|
|
if (hose->first_busno > hose->current_busno)
|
|
hose->current_busno = hose->first_busno;
|
|
#ifdef CONFIG_PCI_PNP
|
|
pciauto_config_init(hose);
|
|
#endif
|
|
return pci_hose_scan_bus(hose, hose->current_busno);
|
|
}
|
|
|
|
void pci_init(void)
|
|
{
|
|
hose_head = NULL;
|
|
|
|
/* now call board specific pci_init()... */
|
|
pci_init_board();
|
|
}
|
|
|
|
/* Returns the address of the requested capability structure within the
|
|
* device's PCI configuration space or 0 in case the device does not
|
|
* support it.
|
|
* */
|
|
int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
|
|
int cap)
|
|
{
|
|
int pos;
|
|
u8 hdr_type;
|
|
|
|
pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
|
|
|
|
pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
|
|
|
|
if (pos)
|
|
pos = pci_find_cap(hose, dev, pos, cap);
|
|
|
|
return pos;
|
|
}
|
|
|
|
/* Find the header pointer to the Capabilities*/
|
|
int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
|
|
u8 hdr_type)
|
|
{
|
|
u16 status;
|
|
|
|
pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
|
|
|
|
if (!(status & PCI_STATUS_CAP_LIST))
|
|
return 0;
|
|
|
|
switch (hdr_type) {
|
|
case PCI_HEADER_TYPE_NORMAL:
|
|
case PCI_HEADER_TYPE_BRIDGE:
|
|
return PCI_CAPABILITY_LIST;
|
|
case PCI_HEADER_TYPE_CARDBUS:
|
|
return PCI_CB_CAPABILITY_LIST;
|
|
default:
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
|
|
{
|
|
int ttl = PCI_FIND_CAP_TTL;
|
|
u8 id;
|
|
u8 next_pos;
|
|
|
|
while (ttl--) {
|
|
pci_hose_read_config_byte(hose, dev, pos, &next_pos);
|
|
if (next_pos < CAP_START_POS)
|
|
break;
|
|
next_pos &= ~3;
|
|
pos = (int) next_pos;
|
|
pci_hose_read_config_byte(hose, dev,
|
|
pos + PCI_CAP_LIST_ID, &id);
|
|
if (id == 0xff)
|
|
break;
|
|
if (id == cap)
|
|
return pos;
|
|
pos += PCI_CAP_LIST_NEXT;
|
|
}
|
|
return 0;
|
|
}
|