mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 03:08:31 +00:00
b71eec3129
Intel Tunnel Creek GPIO register block is compatible with current ich6-gpio driver, except the offset and content of GPIO block base address register in the LPC PCI configuration space are different. Use u16 instead of u32 to store the 16-bit I/O address of the GPIO registers so that it could support both Ivybridge and Tunnel Creek. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
163 lines
4.4 KiB
C
163 lines
4.4 KiB
C
/*
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* Copyright (C) 2014 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <cros_ec.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/arch/pch.h>
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int arch_early_init_r(void)
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{
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if (cros_ec_board_init())
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return -1;
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return 0;
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}
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static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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.gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
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.gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */
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.gpio5 = GPIO_MODE_GPIO, /* SIM_DET */
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.gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */
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.gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */
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.gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */
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.gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
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.gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
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.gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
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.gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
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.gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
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.gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
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.gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
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.gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
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};
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static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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.gpio0 = GPIO_DIR_INPUT,
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.gpio3 = GPIO_DIR_INPUT,
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.gpio5 = GPIO_DIR_INPUT,
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.gpio7 = GPIO_DIR_INPUT,
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.gpio8 = GPIO_DIR_INPUT,
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.gpio9 = GPIO_DIR_INPUT,
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.gpio10 = GPIO_DIR_INPUT,
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.gpio11 = GPIO_DIR_INPUT,
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.gpio12 = GPIO_DIR_INPUT,
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.gpio14 = GPIO_DIR_INPUT,
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.gpio15 = GPIO_DIR_INPUT,
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.gpio21 = GPIO_DIR_INPUT,
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.gpio24 = GPIO_DIR_OUTPUT,
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.gpio28 = GPIO_DIR_INPUT,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_level = {
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.gpio1 = GPIO_LEVEL_HIGH,
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.gpio6 = GPIO_LEVEL_HIGH,
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.gpio24 = GPIO_LEVEL_LOW,
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};
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static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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.gpio7 = GPIO_INVERT,
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.gpio8 = GPIO_INVERT,
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.gpio12 = GPIO_INVERT,
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.gpio14 = GPIO_INVERT,
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.gpio15 = GPIO_INVERT,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_mode = {
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.gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
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.gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
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.gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
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.gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
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.gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
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.gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
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};
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static const struct pch_gpio_set2 pch_gpio_set2_direction = {
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.gpio36 = GPIO_DIR_OUTPUT,
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.gpio41 = GPIO_DIR_INPUT,
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.gpio42 = GPIO_DIR_INPUT,
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.gpio43 = GPIO_DIR_INPUT,
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.gpio57 = GPIO_DIR_INPUT,
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.gpio60 = GPIO_DIR_OUTPUT,
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};
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static const struct pch_gpio_set2 pch_gpio_set2_level = {
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.gpio36 = GPIO_LEVEL_HIGH,
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.gpio60 = GPIO_LEVEL_HIGH,
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};
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static const struct pch_gpio_set3 pch_gpio_set3_mode = {
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};
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static const struct pch_gpio_set3 pch_gpio_set3_direction = {
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};
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static const struct pch_gpio_set3 pch_gpio_set3_level = {
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};
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static const struct pch_gpio_map link_gpio_map = {
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.set1 = {
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.mode = &pch_gpio_set1_mode,
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.direction = &pch_gpio_set1_direction,
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.level = &pch_gpio_set1_level,
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.invert = &pch_gpio_set1_invert,
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},
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.set2 = {
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.mode = &pch_gpio_set2_mode,
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.direction = &pch_gpio_set2_direction,
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.level = &pch_gpio_set2_level,
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},
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.set3 = {
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.mode = &pch_gpio_set3_mode,
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.direction = &pch_gpio_set3_direction,
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.level = &pch_gpio_set3_level,
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},
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};
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int board_early_init_f(void)
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{
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ich_gpio_set_gpio_map(&link_gpio_map);
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return 0;
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}
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void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
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{
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/* GPIO Set 1 */
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if (gpio->set1.level)
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outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
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if (gpio->set1.mode)
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outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
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if (gpio->set1.direction)
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outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
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if (gpio->set1.reset)
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outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
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if (gpio->set1.invert)
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outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
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if (gpio->set1.blink)
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outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
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/* GPIO Set 2 */
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if (gpio->set2.level)
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outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
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if (gpio->set2.mode)
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outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
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if (gpio->set2.direction)
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outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
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if (gpio->set2.reset)
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outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
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/* GPIO Set 3 */
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if (gpio->set3.level)
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outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
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if (gpio->set3.mode)
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outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
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if (gpio->set3.direction)
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outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
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if (gpio->set3.reset)
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outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
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}
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