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f767a4e82e
I2C bus 0 was not initialized correctly. There is an offset between i2c index and the structure number of pad info. So i2c bus 0 can be in an inconsistent state. This problem become visible on B{4,6}50v3 with the CPUC HW watchdog enabled. Sometimes when the CPUC HW watchdog interrupted the boot process, U-Boot was not able to read VPD from I2C/EEPROM and the system failed to boot up again, because a device connected to that bus was stuck in data transfer state (from previous boot attempt) and there was no method to recover (struct mxc_i2c_bus::idle_bus_fn was not set) courtesy of incorrect initialization. Signed-off-by: Dan Cimpoca <dan.I.cimpoca@ge.com> Signed-off-by: Fabien Lahoudere <fabien.lahoudere@collabora.com> |
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bx50v3 | ||
common | ||
mx53ppd |