mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
be71a179bd
Support Andestech eth ftmac100 device tree flow on AG101P/AE3XX platform. Verification: Boot linux kernel via dhcp and bootm ok. NDS32 # setenv bootm_size 0x2000000;setenv fdt_high 0x1f00000; NDS32 # dhcp 0x600000 10.0.4.97:boomimage-310y-ae300-spi.bin BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 BOOTP broadcast 4 DHCP client bound to address 10.0.4.178 (4899 ms) Using mac@e0100000 device TFTP from server 10.0.4.97; our IP address is 10.0.4.178 Filename 'boomimage-310y-ae300-spi.bin'. Load address: 0x600000 Loading: ################################################################# ################################################################# ################################################################# ... ... ################################### 233.4 KiB/s done Bytes transferred = 13872076 (d3abcc hex) NDS32 # dhcp 0x2000000 10.0.4.97:ae300.dtb BOOTP broadcast 1 BOOTP broadcast 2 BOOTP broadcast 3 BOOTP broadcast 4 DHCP client bound to address 10.0.4.178 (4592 ms) Using mac@e0100000 device TFTP from server 10.0.4.97; our IP address is 10.0.4.178 Filename 'ae300.dtb'. Load address: 0x2000000 Loading: # 82 KiB/s done Bytes transferred = 2378 (94a hex) NDS32 # bootm 0x600000 - 0x2000000 Image Name: Created: 2017-03-22 6:52:03 UTC Image Type: NDS32 Linux Kernel Image (uncompressed) Data Size: 13872012 Bytes = 13.2 MiB Load Address: 0000c000 Entry Point: 0000c000 Verifying Checksum ... OK Booting using the fdt blob at 0x2000000 Loading Kernel Image ... OK Loading Device Tree to 01efc000, end 01eff949 ... OK Linux version 3.10.102-20375-gb0034c1-dirty (rick@app09) (gcc version 4.9.3 (2016-07-06_nds32le-linux-glibc-v3_experimental) ) #293 PREEMPT Wed Mar 22 14:49:28 CST 2017 CPU: NDS32 N13, AndesCore ID(wb), CPU_VER 0x0d11103f(id 13, rev 17, cfg 4159) ... ... Signed-off-by: rick <rick@andestech.com>
255 lines
6.3 KiB
C
255 lines
6.3 KiB
C
/*
|
|
* Copyright (C) 2011 Andes Technology Corporation
|
|
* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
|
|
* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef __CONFIG_H
|
|
#define __CONFIG_H
|
|
|
|
#include <asm/arch-ae3xx/ae3xx.h>
|
|
|
|
/*
|
|
* CPU and Board Configuration Options
|
|
*/
|
|
#define CONFIG_USE_INTERRUPT
|
|
|
|
#define CONFIG_SKIP_LOWLEVEL_INIT
|
|
|
|
#define CONFIG_SKIP_TRUNOFF_WATCHDOG
|
|
|
|
#define CONFIG_CMDLINE_EDITING
|
|
#define CONFIG_PANIC_HANG
|
|
|
|
#define CONFIG_SYS_ICACHE_OFF
|
|
#define CONFIG_SYS_DCACHE_OFF
|
|
|
|
#define CONFIG_BOOTP_SEND_HOSTNAME
|
|
#define CONFIG_BOOTP_SERVERIP
|
|
|
|
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
|
|
#define CONFIG_SYS_TEXT_BASE 0x00500000
|
|
#ifdef CONFIG_OF_CONTROL
|
|
#undef CONFIG_OF_SEPARATE
|
|
#define CONFIG_OF_EMBED
|
|
#endif
|
|
#else
|
|
|
|
#define CONFIG_SYS_TEXT_BASE 0x80000000
|
|
#endif
|
|
|
|
/*
|
|
* Timer
|
|
*/
|
|
#define CONFIG_SYS_CLK_FREQ 39062500
|
|
#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
|
|
|
|
/*
|
|
* Use Externel CLOCK or PCLK
|
|
*/
|
|
#undef CONFIG_FTRTC010_EXTCLK
|
|
|
|
#ifndef CONFIG_FTRTC010_EXTCLK
|
|
#define CONFIG_FTRTC010_PCLK
|
|
#endif
|
|
|
|
#ifdef CONFIG_FTRTC010_EXTCLK
|
|
#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
|
|
#else
|
|
#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
|
|
#endif
|
|
|
|
#define TIMER_LOAD_VAL 0xffffffff
|
|
|
|
/*
|
|
* Real Time Clock
|
|
*/
|
|
#define CONFIG_RTC_FTRTC010
|
|
|
|
/*
|
|
* Real Time Clock Divider
|
|
* RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
|
|
*/
|
|
#define OSC_5MHZ (5*1000000)
|
|
#define OSC_CLK (4*OSC_5MHZ)
|
|
#define RTC_DIV_COUNT (0.5) /* Why?? */
|
|
|
|
/*
|
|
* Serial console configuration
|
|
*/
|
|
|
|
/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
|
|
#define CONFIG_CONS_INDEX 1
|
|
#define CONFIG_SYS_NS16550_SERIAL
|
|
#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
|
|
#ifndef CONFIG_DM_SERIAL
|
|
#define CONFIG_SYS_NS16550_REG_SIZE -4
|
|
#endif
|
|
#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
|
|
|
|
/*
|
|
* SD (MMC) controller
|
|
*/
|
|
#define CONFIG_FTSDC010
|
|
#define CONFIG_FTSDC010_NUMBER 1
|
|
#define CONFIG_FTSDC010_SDIO
|
|
|
|
/*
|
|
* Miscellaneous configurable options
|
|
*/
|
|
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
|
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
|
|
|
/* Print Buffer Size */
|
|
#define CONFIG_SYS_PBSIZE \
|
|
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
|
|
|
/* max number of command args */
|
|
#define CONFIG_SYS_MAXARGS 16
|
|
|
|
/* Boot Argument Buffer Size */
|
|
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
|
|
|
/*
|
|
* Size of malloc() pool
|
|
*/
|
|
/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
|
|
#define CONFIG_SYS_MALLOC_LEN (512 << 10)
|
|
|
|
/*
|
|
* Physical Memory Map
|
|
*/
|
|
#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
|
|
|
|
#define PHYS_SDRAM_1 \
|
|
(PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
|
|
|
|
#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
|
|
|
|
#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */
|
|
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
|
|
|
|
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
|
|
|
|
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
|
|
GENERATED_GBL_DATA_SIZE)
|
|
|
|
/*
|
|
* Load address and memory test area should agree with
|
|
* arch/nds32/config.mk. Be careful not to overwrite U-Boot itself.
|
|
*/
|
|
#define CONFIG_SYS_LOAD_ADDR 0x300000
|
|
|
|
/* memtest works on 63 MB in DRAM */
|
|
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
|
|
#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
|
|
|
|
/*
|
|
* Static memory controller configuration
|
|
*/
|
|
#define CONFIG_FTSMC020
|
|
|
|
#ifdef CONFIG_FTSMC020
|
|
#include <faraday/ftsmc020.h>
|
|
|
|
#define CONFIG_SYS_FTSMC020_CONFIGS { \
|
|
{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
|
|
{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
|
|
}
|
|
|
|
#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
|
|
#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
|
|
FTSMC020_BANK_SIZE_32M | \
|
|
FTSMC020_BANK_MBW_32)
|
|
|
|
#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
|
|
FTSMC020_TPR_AST(1) | \
|
|
FTSMC020_TPR_CTW(1) | \
|
|
FTSMC020_TPR_ATI(1) | \
|
|
FTSMC020_TPR_AT2(1) | \
|
|
FTSMC020_TPR_WTC(1) | \
|
|
FTSMC020_TPR_AHT(1) | \
|
|
FTSMC020_TPR_TRNA(1))
|
|
#endif
|
|
|
|
/*
|
|
* FLASH on ADP_AG101P is connected to BANK0
|
|
* Just disalbe the other BANK to avoid detection error.
|
|
*/
|
|
#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
|
|
FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
|
|
FTSMC020_BANK_SIZE_32M | \
|
|
FTSMC020_BANK_MBW_32)
|
|
|
|
#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
|
|
FTSMC020_TPR_CTW(3) | \
|
|
FTSMC020_TPR_ATI(0xf) | \
|
|
FTSMC020_TPR_AT2(3) | \
|
|
FTSMC020_TPR_WTC(3) | \
|
|
FTSMC020_TPR_AHT(3) | \
|
|
FTSMC020_TPR_TRNA(0xf))
|
|
|
|
#define FTSMC020_BANK1_CONFIG (0x00)
|
|
#define FTSMC020_BANK1_TIMING (0x00)
|
|
#endif /* CONFIG_FTSMC020 */
|
|
|
|
/*
|
|
* FLASH and environment organization
|
|
*/
|
|
/* use CFI framework */
|
|
#define CONFIG_SYS_FLASH_CFI
|
|
#define CONFIG_FLASH_CFI_DRIVER
|
|
|
|
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
|
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
|
|
#define CONFIG_SYS_CFI_FLASH_STATUS_POLL
|
|
|
|
/* support JEDEC */
|
|
#ifdef CONFIG_CFI_FLASH
|
|
#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1
|
|
#endif
|
|
|
|
/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
|
|
#define PHYS_FLASH_1 0x88000000 /* BANK 0 */
|
|
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
|
|
#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
|
|
#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
|
|
|
|
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
|
|
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
|
|
|
|
/* max number of memory banks */
|
|
/*
|
|
* There are 4 banks supported for this Controller,
|
|
* but we have only 1 bank connected to flash on board
|
|
*/
|
|
#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT
|
|
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
|
#endif
|
|
#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000}
|
|
|
|
/* max number of sectors on one chip */
|
|
#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2)
|
|
#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
|
|
#define CONFIG_SYS_MAX_FLASH_SECT 512
|
|
|
|
/* environments */
|
|
#define CONFIG_ENV_IS_IN_FLASH
|
|
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
|
|
#define CONFIG_ENV_SIZE 8192
|
|
#define CONFIG_ENV_OVERWRITE
|
|
|
|
/*
|
|
* For booting Linux, the board info and command line data
|
|
* have to be in the first 16 MB of memory, since this is
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
*/
|
|
|
|
/* Initial Memory map for Linux*/
|
|
#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
|
|
/* Increase max gunzip size */
|
|
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
|
|
|
|
#endif /* __CONFIG_H */
|