mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 13:56:30 +00:00
d3daba10f1
AM4372 EPOS EVM has 1GB LPDDR2(Part no: MT42L256M32D2LG-25 WT:A) Adding LPDDR2 init sequence and register details for the same. Below is the brief description of LPDDR2 init sequence: -> Configure VTP -> Configure DDR IO settings -> Disable initialization and refreshes until EMIF registers are programmed. -> Program Timing registers -> Program PHY control and Temp alert and ZQ config registers. -> Enable initialization and refreshes and configure SDRAM CONFIG register -> Wait till initialization is complete and the configure MR registers. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
38 lines
872 B
C
38 lines
872 B
C
/*
|
|
* clocks_am33xx.h
|
|
*
|
|
* AM33xx clock define
|
|
*
|
|
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef _CLOCKS_AM33XX_H_
|
|
#define _CLOCKS_AM33XX_H_
|
|
|
|
/* MAIN PLL Fdll supported frequencies */
|
|
#define MPUPLL_M_1000 1000
|
|
#define MPUPLL_M_800 800
|
|
#define MPUPLL_M_720 720
|
|
#define MPUPLL_M_600 600
|
|
#define MPUPLL_M_550 550
|
|
#define MPUPLL_M_300 300
|
|
|
|
/* MAIN PLL Fdll = 550 MHz, by default */
|
|
#ifndef CONFIG_SYS_MPUCLK
|
|
#define CONFIG_SYS_MPUCLK MPUPLL_M_550
|
|
#endif
|
|
|
|
#define UART_RESET (0x1 << 1)
|
|
#define UART_CLK_RUNNING_MASK 0x1
|
|
#define UART_SMART_IDLE_EN (0x1 << 0x3)
|
|
|
|
#define CM_DLL_CTRL_NO_OVERRIDE 0x0
|
|
#define CM_DLL_READYST 0x4
|
|
|
|
extern void enable_dmm_clocks(void);
|
|
extern const struct dpll_params dpll_core_opp100;
|
|
extern struct dpll_params dpll_mpu_opp100;
|
|
|
|
#endif /* endif _CLOCKS_AM33XX_H_ */
|