mirror of
https://github.com/AsahiLinux/u-boot
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a3df99b50f
The PFD issue is not present on mx6solox, so skip it in this case. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
464 lines
11 KiB
C
464 lines
11 KiB
C
/*
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* (C) Copyright 2007
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* Sascha Hauer, Pengutronix
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*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/armv7.h>
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#include <asm/pl310.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/imx-common/boot_mode.h>
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#include <asm/imx-common/dma.h>
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#include <stdbool.h>
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#include <asm/arch/mxc_hdmi.h>
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#include <asm/arch/crm_regs.h>
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enum ldo_reg {
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LDO_ARM,
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LDO_SOC,
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LDO_PU,
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};
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struct scu_regs {
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u32 ctrl;
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u32 config;
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u32 status;
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u32 invalidate;
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u32 fpga_rev;
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};
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u32 get_cpu_rev(void)
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{
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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u32 reg = readl(&anatop->digprog_sololite);
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u32 type = ((reg >> 16) & 0xff);
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if (type != MXC_CPU_MX6SL) {
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reg = readl(&anatop->digprog);
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struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
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u32 cfg = readl(&scu->config) & 3;
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type = ((reg >> 16) & 0xff);
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if (type == MXC_CPU_MX6DL) {
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if (!cfg)
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type = MXC_CPU_MX6SOLO;
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}
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if (type == MXC_CPU_MX6Q) {
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if (cfg == 1)
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type = MXC_CPU_MX6D;
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}
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}
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reg &= 0xff; /* mx6 silicon revision */
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return (type << 12) | (reg + 0x10);
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}
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#ifdef CONFIG_REVISION_TAG
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u32 __weak get_board_rev(void)
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{
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u32 cpurev = get_cpu_rev();
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u32 type = ((cpurev >> 12) & 0xff);
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if (type == MXC_CPU_MX6SOLO)
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cpurev = (MXC_CPU_MX6DL) << 12 | (cpurev & 0xFFF);
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if (type == MXC_CPU_MX6D)
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cpurev = (MXC_CPU_MX6Q) << 12 | (cpurev & 0xFFF);
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return cpurev;
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}
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#endif
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void init_aips(void)
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{
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struct aipstz_regs *aips1, *aips2;
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#ifdef CONFIG_MX6SX
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struct aipstz_regs *aips3;
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#endif
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aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
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aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
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#ifdef CONFIG_MX6SX
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aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
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#endif
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, &aips1->mprot0);
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writel(0x77777777, &aips1->mprot1);
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writel(0x77777777, &aips2->mprot0);
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writel(0x77777777, &aips2->mprot1);
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/*
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* Set all OPACRx to be non-bufferable, not require
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* supervisor privilege level for access,allow for
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* write access and untrusted master access.
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*/
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writel(0x00000000, &aips1->opacr0);
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writel(0x00000000, &aips1->opacr1);
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writel(0x00000000, &aips1->opacr2);
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writel(0x00000000, &aips1->opacr3);
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writel(0x00000000, &aips1->opacr4);
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writel(0x00000000, &aips2->opacr0);
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writel(0x00000000, &aips2->opacr1);
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writel(0x00000000, &aips2->opacr2);
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writel(0x00000000, &aips2->opacr3);
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writel(0x00000000, &aips2->opacr4);
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#ifdef CONFIG_MX6SX
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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writel(0x77777777, &aips3->mprot0);
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writel(0x77777777, &aips3->mprot1);
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/*
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* Set all OPACRx to be non-bufferable, not require
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* supervisor privilege level for access,allow for
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* write access and untrusted master access.
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*/
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writel(0x00000000, &aips3->opacr0);
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writel(0x00000000, &aips3->opacr1);
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writel(0x00000000, &aips3->opacr2);
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writel(0x00000000, &aips3->opacr3);
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writel(0x00000000, &aips3->opacr4);
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#endif
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}
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static void clear_ldo_ramp(void)
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{
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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int reg;
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/* ROM may modify LDO ramp up time according to fuse setting, so in
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* order to be in the safe side we neeed to reset these settings to
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* match the reset value: 0'b00
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*/
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reg = readl(&anatop->ana_misc2);
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reg &= ~(0x3f << 24);
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writel(reg, &anatop->ana_misc2);
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}
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/*
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* Set the PMU_REG_CORE register
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*
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* Set LDO_SOC/PU/ARM regulators to the specified millivolt level.
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* Possible values are from 0.725V to 1.450V in steps of
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* 0.025V (25mV).
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*/
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static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
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{
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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u32 val, step, old, reg = readl(&anatop->reg_core);
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u8 shift;
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if (mv < 725)
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val = 0x00; /* Power gated off */
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else if (mv > 1450)
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val = 0x1F; /* Power FET switched full on. No regulation */
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else
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val = (mv - 700) / 25;
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clear_ldo_ramp();
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switch (ldo) {
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case LDO_SOC:
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shift = 18;
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break;
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case LDO_PU:
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shift = 9;
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break;
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case LDO_ARM:
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shift = 0;
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break;
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default:
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return -EINVAL;
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}
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old = (reg & (0x1F << shift)) >> shift;
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step = abs(val - old);
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if (step == 0)
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return 0;
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reg = (reg & ~(0x1F << shift)) | (val << shift);
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writel(reg, &anatop->reg_core);
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/*
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* The LDO ramp-up is based on 64 clock cycles of 24 MHz = 2.6 us per
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* step
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*/
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udelay(3 * step);
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return 0;
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}
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static void imx_set_wdog_powerdown(bool enable)
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{
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struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
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struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
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/* Write to the PDE (Power Down Enable) bit */
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writew(enable, &wdog1->wmcr);
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writew(enable, &wdog2->wmcr);
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}
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static void set_ahb_rate(u32 val)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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u32 reg, div;
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div = get_periph_clk() / val - 1;
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reg = readl(&mxc_ccm->cbcdr);
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writel((reg & (~MXC_CCM_CBCDR_AHB_PODF_MASK)) |
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(div << MXC_CCM_CBCDR_AHB_PODF_OFFSET), &mxc_ccm->cbcdr);
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}
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static void clear_mmdc_ch_mask(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* Clear MMDC channel mask */
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writel(0, &mxc_ccm->ccdr);
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}
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int arch_cpu_init(void)
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{
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init_aips();
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/* Need to clear MMDC_CHx_MASK to make warm reset work. */
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clear_mmdc_ch_mask();
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/*
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* When low freq boot is enabled, ROM will not set AHB
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* freq, so we need to ensure AHB freq is 132MHz in such
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* scenario.
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*/
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if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
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set_ahb_rate(132000000);
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imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
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#ifdef CONFIG_APBH_DMA
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/* Start APBH DMA */
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mxs_dma_init();
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#endif
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return 0;
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}
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int board_postclk_init(void)
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{
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set_ldo_voltage(LDO_SOC, 1175); /* Set VDDSOC to 1.175V */
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return 0;
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Avoid random hang when download by usb */
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invalidate_dcache_all();
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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#if defined(CONFIG_FEC_MXC)
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void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
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{
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struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
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struct fuse_bank *bank = &ocotp->bank[4];
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struct fuse_bank4_regs *fuse =
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(struct fuse_bank4_regs *)bank->fuse_regs;
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u32 value = readl(&fuse->mac_addr_high);
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mac[0] = (value >> 8);
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mac[1] = value ;
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value = readl(&fuse->mac_addr_low);
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mac[2] = value >> 24 ;
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mac[3] = value >> 16 ;
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mac[4] = value >> 8 ;
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mac[5] = value ;
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}
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#endif
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void boot_mode_apply(unsigned cfg_val)
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{
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unsigned reg;
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struct src *psrc = (struct src *)SRC_BASE_ADDR;
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writel(cfg_val, &psrc->gpr9);
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reg = readl(&psrc->gpr10);
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if (cfg_val)
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reg |= 1 << 28;
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else
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reg &= ~(1 << 28);
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writel(reg, &psrc->gpr10);
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}
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/*
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* cfg_val will be used for
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* Boot_cfg4[7:0]:Boot_cfg3[7:0]:Boot_cfg2[7:0]:Boot_cfg1[7:0]
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* After reset, if GPR10[28] is 1, ROM will copy GPR9[25:0]
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* to SBMR1, which will determine the boot device.
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*/
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const struct boot_mode soc_boot_modes[] = {
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{"normal", MAKE_CFGVAL(0x00, 0x00, 0x00, 0x00)},
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/* reserved value should start rom usb */
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{"usb", MAKE_CFGVAL(0x01, 0x00, 0x00, 0x00)},
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{"sata", MAKE_CFGVAL(0x20, 0x00, 0x00, 0x00)},
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{"escpi1:0", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x08)},
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{"escpi1:1", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x18)},
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{"escpi1:2", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x28)},
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{"escpi1:3", MAKE_CFGVAL(0x30, 0x00, 0x00, 0x38)},
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/* 4 bit bus width */
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{"esdhc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
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{"esdhc2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
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{"esdhc3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
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{"esdhc4", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
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{NULL, 0},
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};
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void s_init(void)
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{
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struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
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int is_6q = is_cpu_type(MXC_CPU_MX6Q);
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u32 mask480;
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u32 mask528;
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if (is_cpu_type(MXC_CPU_MX6SX))
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return;
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/* Due to hardware limitation, on MX6Q we need to gate/ungate all PFDs
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* to make sure PFD is working right, otherwise, PFDs may
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* not output clock after reset, MX6DL and MX6SL have added 396M pfd
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* workaround in ROM code, as bus clock need it
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*/
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mask480 = ANATOP_PFD_CLKGATE_MASK(0) |
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ANATOP_PFD_CLKGATE_MASK(1) |
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ANATOP_PFD_CLKGATE_MASK(2) |
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ANATOP_PFD_CLKGATE_MASK(3);
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mask528 = ANATOP_PFD_CLKGATE_MASK(0) |
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ANATOP_PFD_CLKGATE_MASK(1) |
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ANATOP_PFD_CLKGATE_MASK(3);
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/*
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* Don't reset PFD2 on DL/S
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*/
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if (is_6q)
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mask528 |= ANATOP_PFD_CLKGATE_MASK(2);
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writel(mask480, &anatop->pfd_480_set);
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writel(mask528, &anatop->pfd_528_set);
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writel(mask480, &anatop->pfd_480_clr);
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writel(mask528, &anatop->pfd_528_clr);
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}
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#ifdef CONFIG_IMX_HDMI
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void imx_enable_hdmi_phy(void)
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{
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struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
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u8 reg;
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reg = readb(&hdmi->phy_conf0);
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reg |= HDMI_PHY_CONF0_PDZ_MASK;
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writeb(reg, &hdmi->phy_conf0);
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udelay(3000);
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reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
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writeb(reg, &hdmi->phy_conf0);
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udelay(3000);
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reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
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writeb(reg, &hdmi->phy_conf0);
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writeb(HDMI_MC_PHYRSTZ_ASSERT, &hdmi->mc_phyrstz);
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}
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void imx_setup_hdmi(void)
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{
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struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
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int reg;
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/* Turn on HDMI PHY clock */
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reg = readl(&mxc_ccm->CCGR2);
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reg |= MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK|
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MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
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writel(reg, &mxc_ccm->CCGR2);
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writeb(HDMI_MC_PHYRSTZ_DEASSERT, &hdmi->mc_phyrstz);
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reg = readl(&mxc_ccm->chsccdr);
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reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK|
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MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK|
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MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
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reg |= (CHSCCDR_PODF_DIVIDE_BY_3
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<< MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
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|(CHSCCDR_IPU_PRE_CLK_540M_PFD
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<< MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
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writel(reg, &mxc_ccm->chsccdr);
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}
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#endif
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#ifndef CONFIG_SYS_L2CACHE_OFF
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#define IOMUXC_GPR11_L2CACHE_AS_OCRAM 0x00000002
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void v7_outer_cache_enable(void)
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{
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struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
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unsigned int val;
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#if defined CONFIG_MX6SL
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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val = readl(&iomux->gpr[11]);
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if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
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/* L2 cache configured as OCRAM, reset it */
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val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
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writel(val, &iomux->gpr[11]);
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}
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#endif
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writel(0x132, &pl310->pl310_tag_latency_ctrl);
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writel(0x132, &pl310->pl310_data_latency_ctrl);
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val = readl(&pl310->pl310_prefetch_ctrl);
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/* Turn on the L2 I/D prefetch */
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val |= 0x30000000;
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/*
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* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
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* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
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* But according to ARM PL310 errata: 752271
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* ID: 752271: Double linefill feature can cause data corruption
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* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
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* Workaround: The only workaround to this erratum is to disable the
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* double linefill feature. This is the default behavior.
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*/
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#ifndef CONFIG_MX6Q
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val |= 0x40800000;
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#endif
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writel(val, &pl310->pl310_prefetch_ctrl);
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val = readl(&pl310->pl310_power_ctrl);
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val |= L2X0_DYNAMIC_CLK_GATING_EN;
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val |= L2X0_STNDBY_MODE_EN;
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writel(val, &pl310->pl310_power_ctrl);
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setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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void v7_outer_cache_disable(void)
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{
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struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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#endif /* !CONFIG_SYS_L2CACHE_OFF */
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