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9675d92027
As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com>
28 lines
570 B
Text
28 lines
570 B
Text
# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2022 StarFive Technology Co., Ltd.
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config STARFIVE_JH7110
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bool
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select ARCH_EARLY_INIT_R
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select CLK_JH7110
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select CPU
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select CPU_RISCV
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select RAM
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select RESET_JH7110
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select SUPPORT_SPL
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select SPL_RAM if SPL
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select SPL_STARFIVE_DDR
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select PINCTRL_STARFIVE_JH7110
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imply MMC
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imply MMC_BROKEN_CD
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imply MMC_SPI
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imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
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imply SIFIVE_CACHE
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imply SIFIVE_CCACHE
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imply SMP
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imply SPI
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imply SPL_CPU
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imply SPL_LOAD_FIT
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imply SPL_OPENSBI
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imply SPL_RISCV_ACLINT
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