mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-20 18:23:08 +00:00
017375cb94
Last use of CONFIG_SYS_GPIO1_PRELIM was removed by commitfae2ea5951("ppc: Remove MPC8349EMDS board and ARCH_MPC8349 support"). Last use of CONFIG_SYS_GPIO2_PRELIM was removed even before by commit6843862342("ppc: Remove caddy2 / vme8349 boards") Those two items were removed from whitelist by commit8cca60a2cb("Kconfig: Remove some symbols from the whitelist") Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Fixes:fae2ea5951("ppc: Remove MPC8349EMDS board and ARCH_MPC8349 support")
411 lines
10 KiB
C
411 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm-offsets.h>
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#include <mpc83xx.h>
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#include <system-constants.h>
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#include <ioports.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#include <fsl_qe.h>
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#ifdef CONFIG_USB_EHCI_FSL
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#include <usb/ehci-ci.h>
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#endif
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#include <linux/delay.h>
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#ifdef CONFIG_QE
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#include <fsl_qe.h>
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#endif
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#include "lblaw/lblaw.h"
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#include "elbc/elbc.h"
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#include "sysio/sysio.h"
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#include "arbiter/arbiter.h"
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#include "initreg/initreg.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_QE
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extern qe_iop_conf_t qe_iop_conf_tab[];
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extern void qe_config_iopin(u8 port, u8 pin, int dir,
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int open_drain, int assign);
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#if !defined(CONFIG_PINCTRL)
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static void config_qe_ioports(void)
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{
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u8 port, pin;
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int dir, open_drain, assign;
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int i;
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for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
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port = qe_iop_conf_tab[i].port;
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pin = qe_iop_conf_tab[i].pin;
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dir = qe_iop_conf_tab[i].dir;
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open_drain = qe_iop_conf_tab[i].open_drain;
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assign = qe_iop_conf_tab[i].assign;
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qe_config_iopin(port, pin, dir, open_drain, assign);
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}
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}
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#endif
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#endif
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/*
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* Breathe some life into the CPU...
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*
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* Set up the memory map,
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* initialize a bunch of registers,
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* initialize the UPM's
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*/
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void cpu_init_f (volatile immap_t * im)
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{
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__be32 sccr_mask =
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#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
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SCCR_ENCCM |
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#endif
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#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
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SCCR_PCICM |
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#endif
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#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
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SCCR_PCIEXP1CM |
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#endif
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#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
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SCCR_PCIEXP2CM |
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#endif
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#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
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SCCR_TSECCM |
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#endif
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#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
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SCCR_TSEC1CM |
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#endif
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#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
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SCCR_TSEC2CM |
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#endif
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#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
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SCCR_TSEC1ON |
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#endif
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#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
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SCCR_TSEC2ON |
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#endif
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#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
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SCCR_USBMPHCM |
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#endif
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#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */
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SCCR_USBDRCM |
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#endif
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#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */
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SCCR_SATACM |
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#endif
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0;
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__be32 sccr_val =
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#ifdef CONFIG_SYS_SCCR_ENCCM /* Encryption clock mode */
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(CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT) |
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#endif
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#ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */
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(CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) |
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#endif
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#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */
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(CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) |
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#endif
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#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */
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(CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) |
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#endif
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#ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */
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(CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) |
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#endif
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#ifdef CFG_SYS_SCCR_TSEC1CM /* TSEC1 clock mode */
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(CFG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT) |
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#endif
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#ifdef CFG_SYS_SCCR_TSEC2CM /* TSEC2 clock mode */
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(CFG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT) |
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#endif
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#ifdef CONFIG_SYS_SCCR_TSEC1ON /* TSEC1 clock switch */
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(CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT) |
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#endif
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#ifdef CONFIG_SYS_SCCR_TSEC2ON /* TSEC2 clock switch */
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(CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT) |
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#endif
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#ifdef CONFIG_SYS_SCCR_USBMPHCM /* USB MPH clock mode */
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(CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT) |
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#endif
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#ifdef CFG_SYS_SCCR_USBDRCM /* USB DR clock mode */
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(CFG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT) |
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#endif
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#ifdef CFG_SYS_SCCR_SATACM /* SATA controller clock mode */
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(CFG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT) |
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#endif
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0;
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/* Pointer is writable since we allocated a register for it */
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gd = (gd_t *)SYS_INIT_SP_ADDR;
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/* global data region was cleared in start.S */
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/* system performance tweaking */
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clrsetbits_be32(&im->arbiter.acr, acr_mask, acr_val);
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clrsetbits_be32(&im->sysconf.spcr, spcr_mask, spcr_val);
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clrsetbits_be32(&im->clk.sccr, sccr_mask, sccr_val);
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/* RSR - Reset Status Register - clear all status (4.6.1.3) */
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gd->arch.reset_status = __raw_readl(&im->reset.rsr);
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__raw_writel(~(RSR_RES), &im->reset.rsr);
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/* AER - Arbiter Event Register - store status */
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gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr);
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gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr);
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/*
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* RMR - Reset Mode Register
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* contains checkstop reset enable (4.6.1.4)
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*/
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__raw_writel(RMR_CSRE & (1<<RMR_CSRE_SHIFT), &im->reset.rmr);
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/* LCRR - Clock Ratio Register (10.3.1.16)
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* write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
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*/
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clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
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__raw_readl(&im->im_lbc.lcrr);
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isync();
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/* Enable Time Base & Decrementer ( so we will have udelay() )*/
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setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
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/* System General Purpose Register */
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#ifdef CFG_SYS_SICRH
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#if defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC8313)
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/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
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__raw_writel((im->sysconf.sicrh & 0x0000000C) | CFG_SYS_SICRH,
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&im->sysconf.sicrh);
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#else
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__raw_writel(CFG_SYS_SICRH, &im->sysconf.sicrh);
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#endif
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#endif
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#ifdef CFG_SYS_SICRL
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__raw_writel(CFG_SYS_SICRL, &im->sysconf.sicrl);
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#endif
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#ifdef CFG_SYS_GPR1
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__raw_writel(CFG_SYS_GPR1, &im->sysconf.gpr1);
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#endif
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#ifdef CFG_SYS_DDRCDR /* DDR control driver register */
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__raw_writel(CFG_SYS_DDRCDR, &im->sysconf.ddrcdr);
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#endif
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#ifdef CFG_SYS_OBIR /* Output buffer impedance register */
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__raw_writel(CFG_SYS_OBIR, &im->sysconf.obir);
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#endif
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#if !defined(CONFIG_PINCTRL)
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#ifdef CONFIG_QE
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/* Config QE ioports */
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config_qe_ioports();
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#endif
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#endif
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/* Set up preliminary BR/OR regs */
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init_early_memctl_regs();
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/* Local Access window setup */
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#if defined(CFG_SYS_LBLAWBAR0_PRELIM) && defined(CFG_SYS_LBLAWAR0_PRELIM)
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im->sysconf.lblaw[0].bar = CFG_SYS_LBLAWBAR0_PRELIM;
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im->sysconf.lblaw[0].ar = CFG_SYS_LBLAWAR0_PRELIM;
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#else
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#error CFG_SYS_LBLAWBAR0_PRELIM & CFG_SYS_LBLAWAR0_PRELIM must be defined
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#endif
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#if defined(CFG_SYS_LBLAWBAR1_PRELIM) && defined(CFG_SYS_LBLAWAR1_PRELIM)
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im->sysconf.lblaw[1].bar = CFG_SYS_LBLAWBAR1_PRELIM;
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im->sysconf.lblaw[1].ar = CFG_SYS_LBLAWAR1_PRELIM;
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#endif
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#if defined(CFG_SYS_LBLAWBAR2_PRELIM) && defined(CFG_SYS_LBLAWAR2_PRELIM)
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im->sysconf.lblaw[2].bar = CFG_SYS_LBLAWBAR2_PRELIM;
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im->sysconf.lblaw[2].ar = CFG_SYS_LBLAWAR2_PRELIM;
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#endif
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#if defined(CFG_SYS_LBLAWBAR3_PRELIM) && defined(CFG_SYS_LBLAWAR3_PRELIM)
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im->sysconf.lblaw[3].bar = CFG_SYS_LBLAWBAR3_PRELIM;
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im->sysconf.lblaw[3].ar = CFG_SYS_LBLAWAR3_PRELIM;
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#endif
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}
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int cpu_init_r (void)
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{
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#ifdef CONFIG_QE
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uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
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qe_init(qe_base);
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qe_reset();
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#endif
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return 0;
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}
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/*
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* Print out the bus arbiter event
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*/
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#if defined(CONFIG_DISPLAY_AER_FULL)
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static int print_83xx_arb_event(int force)
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{
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static char* event[] = {
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"Address Time Out",
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"Data Time Out",
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"Address Only Transfer Type",
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"External Control Word Transfer Type",
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"Reserved Transfer Type",
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"Transfer Error",
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"reserved",
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"reserved"
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};
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static char* master[] = {
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"e300 Core Data Transaction",
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"reserved",
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"e300 Core Instruction Fetch",
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"reserved",
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"TSEC1",
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"TSEC2",
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"USB MPH",
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"USB DR",
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"Encryption Core",
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"I2C Boot Sequencer",
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"JTAG",
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"reserved",
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"eSDHC",
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"PCI1",
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"PCI2",
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"DMA",
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"QUICC Engine 00",
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"QUICC Engine 01",
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"QUICC Engine 10",
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"QUICC Engine 11",
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"reserved",
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"reserved",
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"reserved",
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"reserved",
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"SATA1",
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"SATA2",
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"SATA3",
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"SATA4",
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"reserved",
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"PCI Express 1",
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"PCI Express 2",
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"TDM-DMAC"
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};
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static char *transfer[] = {
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"Address-only, Clean Block",
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"Address-only, lwarx reservation set",
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"Single-beat or Burst write",
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"reserved",
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"Address-only, Flush Block",
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"reserved",
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"Burst write",
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"reserved",
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"Address-only, sync",
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"Address-only, tlbsync",
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"Single-beat or Burst read",
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"Single-beat or Burst read",
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"Address-only, Kill Block",
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"Address-only, icbi",
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"Burst read",
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"reserved",
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"Address-only, eieio",
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"reserved",
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"Single-beat write",
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"reserved",
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"ecowx - Illegal single-beat write",
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"reserved",
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"reserved",
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"reserved",
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"Address-only, TLB Invalidate",
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"reserved",
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"Single-beat or Burst read",
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"reserved",
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"eciwx - Illegal single-beat read",
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"reserved",
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"Burst read",
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"reserved"
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};
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int etype = (gd->arch.arbiter_event_attributes & AEATR_EVENT)
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>> AEATR_EVENT_SHIFT;
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int mstr_id = (gd->arch.arbiter_event_attributes & AEATR_MSTR_ID)
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>> AEATR_MSTR_ID_SHIFT;
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int tbst = (gd->arch.arbiter_event_attributes & AEATR_TBST)
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>> AEATR_TBST_SHIFT;
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int tsize = (gd->arch.arbiter_event_attributes & AEATR_TSIZE)
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>> AEATR_TSIZE_SHIFT;
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int ttype = (gd->arch.arbiter_event_attributes & AEATR_TTYPE)
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>> AEATR_TTYPE_SHIFT;
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if (!force && !gd->arch.arbiter_event_address)
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return 0;
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puts("Arbiter Event Status:\n");
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printf(" Event Address: 0x%08lX\n",
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gd->arch.arbiter_event_address);
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printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
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printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
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printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
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tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
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printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
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return gd->arch.arbiter_event_address;
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}
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#elif defined(CONFIG_DISPLAY_AER_BRIEF)
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static int print_83xx_arb_event(int force)
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{
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if (!force && !gd->arch.arbiter_event_address)
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return 0;
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printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
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gd->arch.arbiter_event_attributes,
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gd->arch.arbiter_event_address);
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return gd->arch.arbiter_event_address;
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}
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#endif /* CONFIG_DISPLAY_AER_xxxx */
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#ifndef CONFIG_CPU_MPC83XX
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/*
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* Figure out the cause of the reset
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*/
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int prt_83xx_rsr(void)
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{
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static struct {
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ulong mask;
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char *desc;
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} bits[] = {
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{
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RSR_SWSR, "Software Soft"}, {
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RSR_SWHR, "Software Hard"}, {
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RSR_JSRS, "JTAG Soft"}, {
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RSR_CSHR, "Check Stop"}, {
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RSR_SWRS, "Software Watchdog"}, {
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RSR_BMRS, "Bus Monitor"}, {
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RSR_SRS, "External/Internal Soft"}, {
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RSR_HRS, "External/Internal Hard"}
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};
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static int n = ARRAY_SIZE(bits);
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ulong rsr = gd->arch.reset_status;
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int i;
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char *sep;
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puts("Reset Status:");
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sep = " ";
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for (i = 0; i < n; i++)
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if (rsr & bits[i].mask) {
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printf("%s%s", sep, bits[i].desc);
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sep = ", ";
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}
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puts("\n");
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#if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
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print_83xx_arb_event(rsr & RSR_BMRS);
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#endif
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puts("\n");
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return 0;
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}
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#endif
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