mirror of
https://github.com/AsahiLinux/u-boot
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a94a4071d4
Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
590 lines
14 KiB
C
590 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* K3: Common Architecture initialization
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <image.h>
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#include <init.h>
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#include <log.h>
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#include <spl.h>
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#include <asm/global_data.h>
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#include <linux/printk.h>
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#include "common.h"
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#include <dm.h>
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#include <remoteproc.h>
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#include <asm/cache.h>
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#include <linux/soc/ti/ti_sci_protocol.h>
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#include <fdt_support.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <fs_loader.h>
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#include <fs.h>
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#include <env.h>
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#include <elf.h>
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#include <soc.h>
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#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
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enum {
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IMAGE_ID_ATF,
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IMAGE_ID_OPTEE,
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IMAGE_ID_SPL,
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IMAGE_ID_DM_FW,
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IMAGE_AMT,
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};
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#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
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static const char *image_os_match[IMAGE_AMT] = {
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"arm-trusted-firmware",
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"tee",
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"U-Boot",
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"DM",
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};
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#endif
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static struct image_info fit_image_info[IMAGE_AMT];
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#endif
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struct ti_sci_handle *get_ti_sci_handle(void)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_FIRMWARE,
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DM_DRIVER_GET(ti_sci), &dev);
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if (ret)
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panic("Failed to get SYSFW (%d)\n", ret);
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return (struct ti_sci_handle *)ti_sci_get_handle_from_sysfw(dev);
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}
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void k3_sysfw_print_ver(void)
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{
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struct ti_sci_handle *ti_sci = get_ti_sci_handle();
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char fw_desc[sizeof(ti_sci->version.firmware_description) + 1];
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/*
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* Output System Firmware version info. Note that since the
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* 'firmware_description' field is not guaranteed to be zero-
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* terminated we manually add a \0 terminator if needed. Further
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* note that we intentionally no longer rely on the extended
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* printf() formatter '%.*s' to not having to require a more
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* full-featured printf() implementation.
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*/
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strncpy(fw_desc, ti_sci->version.firmware_description,
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sizeof(ti_sci->version.firmware_description));
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fw_desc[sizeof(fw_desc) - 1] = '\0';
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printf("SYSFW ABI: %d.%d (firmware rev 0x%04x '%s')\n",
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ti_sci->version.abi_major, ti_sci->version.abi_minor,
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ti_sci->version.firmware_revision, fw_desc);
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}
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void mmr_unlock(uintptr_t base, u32 partition)
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{
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/* Translate the base address */
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uintptr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE;
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/* Unlock the requested partition if locked using two-step sequence */
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writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0);
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writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1);
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}
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bool is_rom_loaded_sysfw(struct rom_extended_boot_data *data)
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{
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if (strncmp(data->header, K3_ROM_BOOT_HEADER_MAGIC, 7))
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return false;
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return data->num_components > 1;
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}
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_K3_EARLY_CONS
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int early_console_init(void)
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{
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struct udevice *dev;
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int ret;
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gd->baudrate = CONFIG_BAUDRATE;
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ret = uclass_get_device_by_seq(UCLASS_SERIAL, CONFIG_K3_EARLY_CONS_IDX,
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&dev);
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if (ret) {
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printf("Error getting serial dev for early console! (%d)\n",
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ret);
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return ret;
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}
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gd->cur_serial_dev = dev;
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gd->flags |= GD_FLG_SERIAL_READY;
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gd->have_console = 1;
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return 0;
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}
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#endif
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#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
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void init_env(void)
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{
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#ifdef CONFIG_SPL_ENV_SUPPORT
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char *part;
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env_init();
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env_relocate();
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switch (spl_boot_device()) {
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case BOOT_DEVICE_MMC2:
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part = env_get("bootpart");
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env_set("storage_interface", "mmc");
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env_set("fw_dev_part", part);
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break;
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case BOOT_DEVICE_SPI:
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env_set("storage_interface", "ubi");
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env_set("fw_ubi_mtdpart", "UBI");
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env_set("fw_ubi_volume", "UBI0");
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break;
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default:
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printf("%s from device %u not supported!\n",
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__func__, spl_boot_device());
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return;
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}
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#endif
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}
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int load_firmware(char *name_fw, char *name_loadaddr, u32 *loadaddr)
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{
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struct udevice *fsdev;
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char *name = NULL;
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int size = 0;
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if (!IS_ENABLED(CONFIG_FS_LOADER))
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return 0;
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*loadaddr = 0;
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#ifdef CONFIG_SPL_ENV_SUPPORT
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switch (spl_boot_device()) {
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case BOOT_DEVICE_MMC2:
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name = env_get(name_fw);
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*loadaddr = env_get_hex(name_loadaddr, *loadaddr);
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break;
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default:
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printf("Loading rproc fw image from device %u not supported!\n",
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spl_boot_device());
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return 0;
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}
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#endif
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if (!*loadaddr)
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return 0;
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if (!get_fs_loader(&fsdev)) {
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size = request_firmware_into_buf(fsdev, name, (void *)*loadaddr,
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0, 0);
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}
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return size;
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}
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void release_resources_for_core_shutdown(void)
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{
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struct ti_sci_handle *ti_sci = get_ti_sci_handle();
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struct ti_sci_dev_ops *dev_ops = &ti_sci->ops.dev_ops;
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struct ti_sci_proc_ops *proc_ops = &ti_sci->ops.proc_ops;
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int ret;
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u32 i;
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/* Iterate through list of devices to put (shutdown) */
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for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
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u32 id = put_device_ids[i];
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ret = dev_ops->put_device(ti_sci, id);
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if (ret)
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panic("Failed to put device %u (%d)\n", id, ret);
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}
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/* Iterate through list of cores to put (shutdown) */
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for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
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u32 id = put_core_ids[i];
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/*
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* Queue up the core shutdown request. Note that this call
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* needs to be followed up by an actual invocation of an WFE
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* or WFI CPU instruction.
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*/
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ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
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if (ret)
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panic("Failed sending core %u shutdown message (%d)\n",
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id, ret);
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}
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}
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void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
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{
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typedef void __noreturn (*image_entry_noargs_t)(void);
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struct ti_sci_handle *ti_sci = get_ti_sci_handle();
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u32 loadaddr = 0;
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int ret, size = 0, shut_cpu = 0;
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/* Release all the exclusive devices held by SPL before starting ATF */
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ti_sci->ops.dev_ops.release_exclusive_devices(ti_sci);
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ret = rproc_init();
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if (ret)
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panic("rproc failed to be initialized (%d)\n", ret);
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init_env();
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if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
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size = load_firmware("name_mcur5f0_0fw", "addr_mcur5f0_0load",
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&loadaddr);
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}
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/*
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* It is assumed that remoteproc device 1 is the corresponding
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* Cortex-A core which runs ATF. Make sure DT reflects the same.
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*/
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if (!fit_image_info[IMAGE_ID_ATF].image_start)
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fit_image_info[IMAGE_ID_ATF].image_start =
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spl_image->entry_point;
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ret = rproc_load(1, fit_image_info[IMAGE_ID_ATF].image_start, 0x200);
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if (ret)
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panic("%s: ATF failed to load on rproc (%d)\n", __func__, ret);
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#if (CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS) && IS_ENABLED(CONFIG_SYS_K3_SPL_ATF))
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/* Authenticate ATF */
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void *image_addr = (void *)fit_image_info[IMAGE_ID_ATF].image_start;
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debug("%s: Authenticating image: addr=%lx, size=%ld, os=%s\n", __func__,
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fit_image_info[IMAGE_ID_ATF].image_start,
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fit_image_info[IMAGE_ID_ATF].image_len,
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image_os_match[IMAGE_ID_ATF]);
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ti_secure_image_post_process(&image_addr,
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(size_t *)&fit_image_info[IMAGE_ID_ATF].image_len);
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/* Authenticate OPTEE */
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image_addr = (void *)fit_image_info[IMAGE_ID_OPTEE].image_start;
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debug("%s: Authenticating image: addr=%lx, size=%ld, os=%s\n", __func__,
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fit_image_info[IMAGE_ID_OPTEE].image_start,
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fit_image_info[IMAGE_ID_OPTEE].image_len,
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image_os_match[IMAGE_ID_OPTEE]);
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ti_secure_image_post_process(&image_addr,
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(size_t *)&fit_image_info[IMAGE_ID_OPTEE].image_len);
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#endif
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if (!fit_image_info[IMAGE_ID_DM_FW].image_len &&
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!(size > 0 && valid_elf_image(loadaddr))) {
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shut_cpu = 1;
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goto start_arm64;
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}
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if (!fit_image_info[IMAGE_ID_DM_FW].image_start) {
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loadaddr = load_elf_image_phdr(loadaddr);
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} else {
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loadaddr = fit_image_info[IMAGE_ID_DM_FW].image_start;
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if (valid_elf_image(loadaddr))
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loadaddr = load_elf_image_phdr(loadaddr);
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}
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debug("%s: jumping to address %x\n", __func__, loadaddr);
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start_arm64:
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/* Add an extra newline to differentiate the ATF logs from SPL */
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printf("Starting ATF on ARM64 core...\n\n");
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ret = rproc_start(1);
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if (ret)
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panic("%s: ATF failed to start on rproc (%d)\n", __func__, ret);
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if (shut_cpu) {
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debug("Shutting down...\n");
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release_resources_for_core_shutdown();
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while (1)
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asm volatile("wfe");
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}
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image_entry_noargs_t image_entry = (image_entry_noargs_t)loadaddr;
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image_entry();
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}
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#endif
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#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
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void board_fit_image_post_process(const void *fit, int node, void **p_image,
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size_t *p_size)
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{
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#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
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int len;
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int i;
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const char *os;
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u32 addr;
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os = fdt_getprop(fit, node, "os", &len);
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addr = fdt_getprop_u32_default_node(fit, node, 0, "entry", -1);
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debug("%s: processing image: addr=%x, size=%d, os=%s\n", __func__,
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addr, *p_size, os);
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for (i = 0; i < IMAGE_AMT; i++) {
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if (!strcmp(os, image_os_match[i])) {
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fit_image_info[i].image_start = addr;
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fit_image_info[i].image_len = *p_size;
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debug("%s: matched image for ID %d\n", __func__, i);
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break;
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}
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}
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/*
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* Only DM and the DTBs are being authenticated here,
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* rest will be authenticated when A72 cluster is up
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*/
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if ((i != IMAGE_ID_ATF) && (i != IMAGE_ID_OPTEE))
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#endif
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{
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ti_secure_image_check_binary(p_image, p_size);
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ti_secure_image_post_process(p_image, p_size);
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}
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#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
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else
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ti_secure_image_check_binary(p_image, p_size);
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#endif
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}
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#endif
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#ifndef CONFIG_SYSRESET
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void reset_cpu(void)
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{
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}
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#endif
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enum k3_device_type get_device_type(void)
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{
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u32 sys_status = readl(K3_SEC_MGR_SYS_STATUS);
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u32 sys_dev_type = (sys_status & SYS_STATUS_DEV_TYPE_MASK) >>
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SYS_STATUS_DEV_TYPE_SHIFT;
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u32 sys_sub_type = (sys_status & SYS_STATUS_SUB_TYPE_MASK) >>
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SYS_STATUS_SUB_TYPE_SHIFT;
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switch (sys_dev_type) {
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case SYS_STATUS_DEV_TYPE_GP:
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return K3_DEVICE_TYPE_GP;
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case SYS_STATUS_DEV_TYPE_TEST:
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return K3_DEVICE_TYPE_TEST;
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case SYS_STATUS_DEV_TYPE_EMU:
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return K3_DEVICE_TYPE_EMU;
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case SYS_STATUS_DEV_TYPE_HS:
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if (sys_sub_type == SYS_STATUS_SUB_TYPE_VAL_FS)
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return K3_DEVICE_TYPE_HS_FS;
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else
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return K3_DEVICE_TYPE_HS_SE;
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default:
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return K3_DEVICE_TYPE_BAD;
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}
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}
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#if defined(CONFIG_DISPLAY_CPUINFO)
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static const char *get_device_type_name(void)
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{
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enum k3_device_type type = get_device_type();
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switch (type) {
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case K3_DEVICE_TYPE_GP:
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return "GP";
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case K3_DEVICE_TYPE_TEST:
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return "TEST";
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case K3_DEVICE_TYPE_EMU:
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return "EMU";
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case K3_DEVICE_TYPE_HS_FS:
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return "HS-FS";
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case K3_DEVICE_TYPE_HS_SE:
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return "HS-SE";
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default:
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return "BAD";
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}
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}
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int print_cpuinfo(void)
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{
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struct udevice *soc;
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char name[64];
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int ret;
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printf("SoC: ");
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ret = soc_get(&soc);
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if (ret) {
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printf("UNKNOWN\n");
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return 0;
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}
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ret = soc_get_family(soc, name, 64);
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if (!ret) {
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printf("%s ", name);
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}
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ret = soc_get_revision(soc, name, 64);
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if (!ret) {
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printf("%s ", name);
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}
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printf("%s\n", get_device_type_name());
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return 0;
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}
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#endif
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#ifdef CONFIG_ARM64
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void board_prep_linux(struct bootm_headers *images)
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{
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debug("Linux kernel Image start = 0x%lx end = 0x%lx\n",
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images->os.start, images->os.end);
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__asm_flush_dcache_range(images->os.start,
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ROUND(images->os.end,
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CONFIG_SYS_CACHELINE_SIZE));
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}
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#endif
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#ifdef CONFIG_CPU_V7R
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void disable_linefill_optimization(void)
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{
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u32 actlr;
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/*
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* On K3 devices there are 2 conditions where R5F can deadlock:
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* 1.When software is performing series of store operations to
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* cacheable write back/write allocate memory region and later
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* on software execute barrier operation (DSB or DMB). R5F may
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* hang at the barrier instruction.
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* 2.When software is performing a mix of load and store operations
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* within a tight loop and store operations are all writing to
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* cacheable write back/write allocates memory regions, R5F may
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* hang at one of the load instruction.
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*
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* To avoid the above two conditions disable linefill optimization
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* inside Cortex R5F.
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*/
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asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (actlr));
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actlr |= (1 << 13); /* Set DLFO bit */
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asm("mcr p15, 0, %0, c1, c0, 1" : : "r" (actlr));
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}
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#endif
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static void remove_fwl_regions(struct fwl_data fwl_data, size_t num_regions,
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enum k3_firewall_region_type fwl_type)
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{
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struct ti_sci_fwl_ops *fwl_ops;
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struct ti_sci_handle *ti_sci;
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struct ti_sci_msg_fwl_region region;
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size_t j;
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ti_sci = get_ti_sci_handle();
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fwl_ops = &ti_sci->ops.fwl_ops;
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for (j = 0; j < fwl_data.regions; j++) {
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region.fwl_id = fwl_data.fwl_id;
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region.region = j;
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region.n_permission_regs = 3;
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fwl_ops->get_fwl_region(ti_sci, ®ion);
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/* Don't disable the background regions */
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if (region.control != 0 &&
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((region.control >> K3_FIREWALL_BACKGROUND_BIT) & 1) == fwl_type) {
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pr_debug("Attempting to disable firewall %5d (%25s)\n",
|
|
region.fwl_id, fwl_data.name);
|
|
region.control = 0;
|
|
|
|
if (fwl_ops->set_fwl_region(ti_sci, ®ion))
|
|
pr_err("Could not disable firewall %5d (%25s)\n",
|
|
region.fwl_id, fwl_data.name);
|
|
}
|
|
}
|
|
}
|
|
|
|
void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size)
|
|
{
|
|
size_t i;
|
|
|
|
for (i = 0; i < fwl_data_size; i++) {
|
|
remove_fwl_regions(fwl_data[i], fwl_data[i].regions,
|
|
K3_FIREWALL_REGION_FOREGROUND);
|
|
remove_fwl_regions(fwl_data[i], fwl_data[i].regions,
|
|
K3_FIREWALL_REGION_BACKGROUND);
|
|
}
|
|
}
|
|
|
|
void spl_enable_dcache(void)
|
|
{
|
|
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
|
|
phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
|
|
|
|
dram_init();
|
|
|
|
/* reserve TLB table */
|
|
gd->arch.tlb_size = PGTABLE_SIZE;
|
|
|
|
ram_top += get_effective_memsize();
|
|
/* keep ram_top in the 32-bit address space */
|
|
if (ram_top >= 0x100000000)
|
|
ram_top = (phys_addr_t) 0x100000000;
|
|
|
|
gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
|
|
gd->arch.tlb_addr &= ~(0x10000 - 1);
|
|
debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
|
|
gd->arch.tlb_addr + gd->arch.tlb_size);
|
|
gd->relocaddr = gd->arch.tlb_addr;
|
|
|
|
dcache_enable();
|
|
#endif
|
|
}
|
|
|
|
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
|
|
void spl_board_prepare_for_boot(void)
|
|
{
|
|
dcache_disable();
|
|
}
|
|
|
|
void spl_board_prepare_for_linux(void)
|
|
{
|
|
dcache_disable();
|
|
}
|
|
#endif
|
|
|
|
int misc_init_r(void)
|
|
{
|
|
if (IS_ENABLED(CONFIG_TI_AM65_CPSW_NUSS)) {
|
|
struct udevice *dev;
|
|
int ret;
|
|
|
|
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
|
DM_DRIVER_GET(am65_cpsw_nuss),
|
|
&dev);
|
|
if (ret)
|
|
printf("Failed to probe am65_cpsw_nuss driver\n");
|
|
}
|
|
|
|
/* Default FIT boot on HS-SE devices */
|
|
if (get_device_type() == K3_DEVICE_TYPE_HS_SE)
|
|
env_set("boot_fit", "1");
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* do_board_detect() - Detect board description
|
|
*
|
|
* Function to detect board description. This is expected to be
|
|
* overridden in the SoC family board file where desired.
|
|
*/
|
|
void __weak do_board_detect(void)
|
|
{
|
|
}
|