mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 09:48:16 +00:00
7dc358bb0d
Now that all boards have been converted, remove old config code and the config option for the new style. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
460 lines
13 KiB
C
460 lines
13 KiB
C
/*
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* Copyright 2007
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* Robert Lazarski, Instituto Atlantico, robertlazarski@gmail.com
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*
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* Copyright 2004, 2007 Freescale Semiconductor.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* atum8548 board configuration file
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*
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* Please refer to doc/README.atum8548 for more info.
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* Debug Options, Disable in production
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#define ET_DEBUG 1
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#define CONFIG_PANIC_HANG 1
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#define DEBUG 1
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*/
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/* CPLD Configuration Options */
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#define MPC85xx_ATUM_CLKOCR 0x80000002
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
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#define CONFIG_MPC8548 1 /* MPC8548 specific */
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#define CONFIG_PCI 1 /* enable any pci type devices */
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#define CONFIG_PCI1 1 /* PCI controller 1 */
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#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
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#define CONFIG_PCI2 1 /* PCI controller 2 */
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#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
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#define CONFIG_TSEC_ENET 1 /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/
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#undef CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
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#define CONFIG_DDR_ECC /* only for ECC DDR module */
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
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#define CONFIG_SYS_CLK_FREQ 33000000
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
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/*
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* Only possible on E500 Version 2 or newer cores.
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*/
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#define CONFIG_ENABLE_36BIT_PHYS 1
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#define CONFIG_CMD_SDRAM 1 /* SDRAM DIMM SPD info printout */
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#define CONFIG_ENABLE_36BIT_PHYS 1
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#undef CFG_DRAM_TEST
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#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00400000
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
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#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
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#define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */
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#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
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#define CFG_PCI2_ADDR (CFG_CCSRBAR+0x9000)
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#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
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/*
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* DDR Setup
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*/
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#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
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#if defined(CONFIG_SPD_EEPROM)
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/*
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* Determine DDR configuration from I2C interface.
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*/
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#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
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#else
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/*
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* Manually set up DDR parameters
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*/
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#define CFG_SDRAM_SIZE 1024 /* DDR is 1024MB */
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#define CFG_DDR_CS0_BNDS 0x0000000f /* 0-1024 */
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#define CFG_DDR_CS0_CONFIG 0x80000102
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#define CFG_DDR_TIMING_0 0x00260802
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#define CFG_DDR_TIMING_1 0x38355322
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#define CFG_DDR_TIMING_2 0x039048c7
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#define CFG_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
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#define CFG_DDR_MODE 0x00000432
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#define CFG_DDR_INTERVAL 0x05150100
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#define DDR_SDRAM_CFG 0x43000000
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#endif
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#undef CONFIG_CLOCKS_IN_MHZ
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/*
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* Local Bus Definitions
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*/
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/*
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* FLASH on the Local Bus
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* based on flash chip S29GL01GP
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* One bank, 128M, using the CFI driver.
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* Boot from BR0 bank at 0xf800_0000
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*
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* BR0:
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* Base address 0 = 0xF8000000 = BR0[0:16] = 1111 1000 0000 0000 0
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* Port Size = 16 bits = BRx[19:20] = 10
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* Use GPCM = BRx[24:26] = 000
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* Valid = BRx[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1000 0000 0000 0001 0000 0000 0001 = f8001001 BR0
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*
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* OR0:
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* Addr Mask = 128M = ORx[0:16] = 1111 1000 0000 0000 0
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* Reserved ORx[17:18] = 00
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* CSNT = ORx[20] = 1
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* ACS = half cycle delay = ORx[21:22] = 11
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* SCY = 6 = ORx[24:27] = 0110
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* TRLX = use relaxed timing = ORx[29] = 1
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* EAD = use external address latch delay = OR[31] = 1
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*
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* 0 4 8 12 16 20 24 28
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* 1111 1000 0000 0000 0000 1110 0110 0101 = f8000E65 ORx
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*/
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#define CFG_BOOT_BLOCK 0xf8000000 /* boot TLB block */
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#define CFG_FLASH_BASE CFG_BOOT_BLOCK /* start of FLASH 128M */
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#define CFG_BR0_PRELIM 0xf8001001
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#define CFG_OR0_PRELIM 0xf8000E65
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#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
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#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 512000 /* Flash Erase Timeout (ms) */
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#define CFG_FLASH_WRITE_TOUT 8000 /* Flash Write Timeout (ms) */
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#define CFG_FLASH_CFI_DRIVER 1
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#define CFG_FLASH_CFI 1
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#define CFG_FLASH_EMPTY_INFO
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/*
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* Flash on the LocalBus
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*/
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#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
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/* Memory */
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#define CFG_INIT_RAM_LOCK 1
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#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
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#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
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#define CFG_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
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#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK get_bus_freq(0)
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
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#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
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/* Use the HUSH parser */
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#define CFG_HUSH_PARSER
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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/*
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* I2C
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*/
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#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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#define CONFIG_HARD_I2C /* I2C with hardware support*/
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3000
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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#define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */
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#define CFG_PCI1_MEM_BASE 0x80000000
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#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
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#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CFG_PCI1_IO_BASE 0x00000000
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#define CFG_PCI1_IO_PHYS 0xe2000000
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#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
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#ifdef CONFIG_PCI2
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#define CFG_PCI2_MEM_BASE 0xC0000000
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#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
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#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
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#define CFG_PCI2_IO_BASE 0x00000000
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#define CFG_PCI2_IO_PHYS 0xe2800000
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#define CFG_PCI2_IO_SIZE 0x00100000 /* 1M */
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#endif
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#ifdef CONFIG_PCIE1
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#define CFG_PCIE1_MEM_BASE 0xa0000000
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#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
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#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */
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#define CFG_PCIE1_IO_BASE 0x00000000
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#define CFG_PCIE1_IO_PHYS 0xe3000000
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#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
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#endif
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#if !defined(CONFIG_PCI_PNP)
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#define PCI_ENET0_IOADDR 0xe0000000
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#define PCI_ENET0_MEMADDR 0xe0000000
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#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
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#endif
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#if defined(CONFIG_PCI)
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#undef CONFIG_EEPRO100
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#undef CONFIG_TULIP
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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/* PCI view of System Memory */
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#define CFG_PCI_MEMORY_BUS 0x00000000
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#define CFG_PCI_MEMORY_PHYS 0x00000000
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#define CFG_PCI_MEMORY_SIZE 0x80000000
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_TSEC_ENET)
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC1"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "eTSEC2"
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#define CONFIG_TSEC4 1
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#define CONFIG_TSEC4_NAME "eTSEC3"
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#undef CONFIG_MPC85XX_FEC
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#define TSEC1_PHY_ADDR 0
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#define TSEC2_PHY_ADDR 1
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#define TSEC3_PHY_ADDR 2
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#define TSEC4_PHY_ADDR 3
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define TSEC4_PHYIDX 0
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#define TSEC1_FLAGS TSEC_GIGABIT
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#define TSEC2_FLAGS TSEC_GIGABIT
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#define TSEC3_FLAGS TSEC_GIGABIT
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#define TSEC4_FLAGS TSEC_GIGABIT
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/* Options are: eTSEC[0-3] */
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#define CONFIG_ETHPRIME "eTSEC2"
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#endif /* CONFIG_TSEC_ENET */
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/*
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* Environment
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*/
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
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#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
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#define CFG_ENV_SIZE 0x2000
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_LOAD_ADDR 0x2000000 /* default load address */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Environment Configuration
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*/
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/* The mac addresses for all ethernet interface */
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_HAS_ETH0
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#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
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#define CONFIG_HAS_ETH1
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#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
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#define CONFIG_HAS_ETH2
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#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
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#define CONFIG_HAS_ETH3
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#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
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#endif
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#define CONFIG_IPADDR 10.101.43.142
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#define CONFIG_HOSTNAME atum
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#define CONFIG_ROOTPATH /nfsroot
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#define CONFIG_BOOTFILE /tftpboot/uImage.atum
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#define CONFIG_UBOOTPATH /tftpboot/uboot.bin /* TFTP server */
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#define CONFIG_SERVERIP 10.101.43.10
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#define CONFIG_GATEWAYIP 10.101.45.1
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#define CONFIG_NETMASK 255.255.248.0
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#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
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#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
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#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $dtbaddr $dtbfile;" \
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"bootm $loadaddr - $dtbaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $dtbaddr $dtbfile;" \
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"bootm $loadaddr $ramdiskaddr $dtbaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
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#endif /* __CONFIG_H */
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