mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-07 13:44:29 +00:00
9eef56dbe3
Move env_get_ulong() over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
402 lines
9.1 KiB
C
402 lines
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* K2G EVM : Board initialization
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*
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* (C) Copyright 2015
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* Texas Instruments Incorporated, <www.ti.com>
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*/
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#include <common.h>
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#include <env.h>
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#include <asm/arch/clock.h>
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#include <asm/ti-common/keystone_net.h>
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#include <asm/arch/psc_defs.h>
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#include <asm/arch/mmc_host_def.h>
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#include <fdtdec.h>
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#include <i2c.h>
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#include <remoteproc.h>
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#include "mux-k2g.h"
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#include "../common/board_detect.h"
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#define K2G_GP_AUDIO_CODEC_ADDRESS 0x1B
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const unsigned int sysclk_array[MAX_SYSCLK] = {
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19200000,
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24000000,
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25000000,
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26000000,
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};
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unsigned int get_external_clk(u32 clk)
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{
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unsigned int clk_freq;
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u8 sysclk_index = get_sysclk_index();
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switch (clk) {
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case sys_clk:
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clk_freq = sysclk_array[sysclk_index];
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break;
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case pa_clk:
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clk_freq = sysclk_array[sysclk_index];
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break;
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case tetris_clk:
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clk_freq = sysclk_array[sysclk_index];
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break;
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case ddr3a_clk:
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clk_freq = sysclk_array[sysclk_index];
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break;
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case uart_clk:
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clk_freq = sysclk_array[sysclk_index];
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break;
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default:
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clk_freq = 0;
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break;
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}
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return clk_freq;
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}
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int speeds[DEVSPEED_NUMSPDS] = {
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SPD400,
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SPD600,
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SPD800,
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SPD900,
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SPD1000,
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SPD900,
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SPD800,
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SPD600,
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SPD400,
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SPD200,
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};
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static int dev_speeds[DEVSPEED_NUMSPDS] = {
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SPD600,
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SPD800,
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SPD900,
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SPD1000,
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SPD900,
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SPD800,
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SPD600,
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SPD400,
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};
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static struct pll_init_data main_pll_config[MAX_SYSCLK][NUM_SPDS] = {
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[SYSCLK_19MHz] = {
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[SPD400] = {MAIN_PLL, 125, 3, 2},
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[SPD600] = {MAIN_PLL, 125, 2, 2},
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[SPD800] = {MAIN_PLL, 250, 3, 2},
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[SPD900] = {MAIN_PLL, 187, 2, 2},
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[SPD1000] = {MAIN_PLL, 104, 1, 2},
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},
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[SYSCLK_24MHz] = {
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[SPD400] = {MAIN_PLL, 100, 3, 2},
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[SPD600] = {MAIN_PLL, 300, 6, 2},
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[SPD800] = {MAIN_PLL, 200, 3, 2},
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[SPD900] = {MAIN_PLL, 75, 1, 2},
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[SPD1000] = {MAIN_PLL, 250, 3, 2},
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},
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[SYSCLK_25MHz] = {
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[SPD400] = {MAIN_PLL, 32, 1, 2},
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[SPD600] = {MAIN_PLL, 48, 1, 2},
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[SPD800] = {MAIN_PLL, 64, 1, 2},
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[SPD900] = {MAIN_PLL, 72, 1, 2},
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[SPD1000] = {MAIN_PLL, 80, 1, 2},
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},
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[SYSCLK_26MHz] = {
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[SPD400] = {MAIN_PLL, 400, 13, 2},
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[SPD600] = {MAIN_PLL, 230, 5, 2},
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[SPD800] = {MAIN_PLL, 123, 2, 2},
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[SPD900] = {MAIN_PLL, 69, 1, 2},
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[SPD1000] = {MAIN_PLL, 384, 5, 2},
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},
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};
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static struct pll_init_data tetris_pll_config[MAX_SYSCLK][NUM_SPDS] = {
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[SYSCLK_19MHz] = {
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[SPD200] = {TETRIS_PLL, 625, 6, 10},
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[SPD400] = {TETRIS_PLL, 125, 1, 6},
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[SPD600] = {TETRIS_PLL, 125, 1, 4},
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[SPD800] = {TETRIS_PLL, 333, 2, 4},
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[SPD900] = {TETRIS_PLL, 187, 2, 2},
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[SPD1000] = {TETRIS_PLL, 104, 1, 2},
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},
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[SYSCLK_24MHz] = {
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[SPD200] = {TETRIS_PLL, 250, 3, 10},
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[SPD400] = {TETRIS_PLL, 100, 1, 6},
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[SPD600] = {TETRIS_PLL, 100, 1, 4},
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[SPD800] = {TETRIS_PLL, 400, 3, 4},
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[SPD900] = {TETRIS_PLL, 75, 1, 2},
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[SPD1000] = {TETRIS_PLL, 250, 3, 2},
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},
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[SYSCLK_25MHz] = {
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[SPD200] = {TETRIS_PLL, 80, 1, 10},
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[SPD400] = {TETRIS_PLL, 96, 1, 6},
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[SPD600] = {TETRIS_PLL, 96, 1, 4},
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[SPD800] = {TETRIS_PLL, 128, 1, 4},
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[SPD900] = {TETRIS_PLL, 72, 1, 2},
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[SPD1000] = {TETRIS_PLL, 80, 1, 2},
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},
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[SYSCLK_26MHz] = {
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[SPD200] = {TETRIS_PLL, 307, 4, 10},
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[SPD400] = {TETRIS_PLL, 369, 4, 6},
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[SPD600] = {TETRIS_PLL, 369, 4, 4},
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[SPD800] = {TETRIS_PLL, 123, 1, 4},
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[SPD900] = {TETRIS_PLL, 69, 1, 2},
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[SPD1000] = {TETRIS_PLL, 384, 5, 2},
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},
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};
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static struct pll_init_data uart_pll_config[MAX_SYSCLK] = {
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[SYSCLK_19MHz] = {UART_PLL, 160, 1, 8},
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[SYSCLK_24MHz] = {UART_PLL, 128, 1, 8},
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[SYSCLK_25MHz] = {UART_PLL, 768, 5, 10},
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[SYSCLK_26MHz] = {UART_PLL, 384, 13, 2},
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};
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static struct pll_init_data nss_pll_config[MAX_SYSCLK] = {
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[SYSCLK_19MHz] = {NSS_PLL, 625, 6, 2},
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[SYSCLK_24MHz] = {NSS_PLL, 250, 3, 2},
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[SYSCLK_25MHz] = {NSS_PLL, 80, 1, 2},
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[SYSCLK_26MHz] = {NSS_PLL, 1000, 13, 2},
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};
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static struct pll_init_data ddr3_pll_config_800[MAX_SYSCLK] = {
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[SYSCLK_19MHz] = {DDR3A_PLL, 167, 1, 16},
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[SYSCLK_24MHz] = {DDR3A_PLL, 133, 1, 16},
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[SYSCLK_25MHz] = {DDR3A_PLL, 128, 1, 16},
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[SYSCLK_26MHz] = {DDR3A_PLL, 123, 1, 16},
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};
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static struct pll_init_data ddr3_pll_config_1066[MAX_SYSCLK] = {
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[SYSCLK_19MHz] = {DDR3A_PLL, 194, 1, 14},
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[SYSCLK_24MHz] = {DDR3A_PLL, 156, 1, 14},
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[SYSCLK_25MHz] = {DDR3A_PLL, 149, 1, 14},
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[SYSCLK_26MHz] = {DDR3A_PLL, 144, 1, 14},
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};
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struct pll_init_data *get_pll_init_data(int pll)
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{
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int speed;
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struct pll_init_data *data = NULL;
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u8 sysclk_index = get_sysclk_index();
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switch (pll) {
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case MAIN_PLL:
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speed = get_max_dev_speed(dev_speeds);
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data = &main_pll_config[sysclk_index][speed];
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break;
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case TETRIS_PLL:
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speed = get_max_arm_speed(speeds);
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data = &tetris_pll_config[sysclk_index][speed];
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break;
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case NSS_PLL:
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data = &nss_pll_config[sysclk_index];
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break;
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case UART_PLL:
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data = &uart_pll_config[sysclk_index];
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break;
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case DDR3_PLL:
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if (cpu_revision() & CPU_66AK2G1x) {
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speed = get_max_arm_speed(speeds);
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if (speed == SPD1000)
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data = &ddr3_pll_config_1066[sysclk_index];
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else
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data = &ddr3_pll_config_800[sysclk_index];
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} else {
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data = &ddr3_pll_config_800[sysclk_index];
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}
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break;
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default:
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data = NULL;
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}
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return data;
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}
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s16 divn_val[16] = {
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
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};
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#if defined(CONFIG_MMC)
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int board_mmc_init(bd_t *bis)
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{
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if (psc_enable_module(KS2_LPSC_MMC)) {
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printf("%s module enabled failed\n", __func__);
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return -1;
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}
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if (board_is_k2g_gp() || board_is_k2g_g1())
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omap_mmc_init(0, 0, 0, -1, -1);
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omap_mmc_init(1, 0, 0, -1, -1);
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return 0;
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}
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#endif
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#if defined(CONFIG_MULTI_DTB_FIT)
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int board_fit_config_name_match(const char *name)
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{
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bool eeprom_read = board_ti_was_eeprom_read();
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if (!strcmp(name, "keystone-k2g-generic") && !eeprom_read)
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return 0;
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else if (!strcmp(name, "keystone-k2g-evm") &&
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(board_ti_is("66AK2GGP") || board_ti_is("66AK2GG1")))
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return 0;
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else if (!strcmp(name, "keystone-k2g-ice") && board_ti_is("66AK2GIC"))
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return 0;
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else
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return -1;
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}
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#endif
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#if defined(CONFIG_DTB_RESELECT)
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static int k2g_alt_board_detect(void)
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{
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#ifndef CONFIG_DM_I2C
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int rc;
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rc = i2c_set_bus_num(1);
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if (rc)
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return rc;
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rc = i2c_probe(K2G_GP_AUDIO_CODEC_ADDRESS);
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if (rc)
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return rc;
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#else
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struct udevice *bus, *dev;
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int rc;
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rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus);
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if (rc)
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return rc;
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rc = dm_i2c_probe(bus, K2G_GP_AUDIO_CODEC_ADDRESS, 0, &dev);
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if (rc)
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return rc;
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#endif
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ti_i2c_eeprom_am_set("66AK2GGP", "1.0X");
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return 0;
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}
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static void k2g_reset_mux_config(void)
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{
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/* Unlock the reset mux register */
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clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
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/* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
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clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
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RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
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/* lock the reset mux register to prevent any spurious writes. */
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setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
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}
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int embedded_dtb_select(void)
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{
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int rc;
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rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
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CONFIG_EEPROM_CHIP_ADDRESS);
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if (rc) {
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rc = k2g_alt_board_detect();
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if (rc) {
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printf("Unable to do board detection\n");
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return -1;
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}
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}
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fdtdec_setup();
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k2g_mux_config();
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k2g_reset_mux_config();
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if (board_is_k2g_gp() || board_is_k2g_g1()) {
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/* deassert FLASH_HOLD */
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clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
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BIT(9));
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setbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_SETDATA_OFFSET,
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BIT(9));
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} else if (board_is_k2g_ice()) {
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/* GBE Phy workaround. For Phy to latch the input
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* configuration, a GPIO reset is asserted at the
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* Phy reset pin to latch configuration correctly after SoC
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* reset. GPIO0 Pin 10 (Ball AA20) is used for this on ICE
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* board. Just do a low to high transition.
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*/
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clrbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_DIR_OFFSET,
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BIT(10));
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setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_CLRDATA_OFFSET,
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BIT(10));
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/* Delay just to get a transition to high */
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udelay(100);
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setbits_le32(K2G_GPIO0_BANK0_BASE + K2G_GPIO_SETDATA_OFFSET,
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BIT(10));
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}
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return 0;
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}
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#endif
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_TI_I2C_BOARD_DETECT)
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int rc;
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rc = ti_i2c_eeprom_am_get(CONFIG_EEPROM_BUS_ADDRESS,
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CONFIG_EEPROM_CHIP_ADDRESS);
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if (rc)
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printf("ti_i2c_eeprom_init failed %d\n", rc);
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board_ti_set_ethaddr(1);
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#endif
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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if (board_is_k2g_gp())
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env_set("board_name", "66AK2GGP\0");
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else if (board_is_k2g_g1())
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env_set("board_name", "66AK2GG1\0");
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else if (board_is_k2g_ice())
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env_set("board_name", "66AK2GIC\0");
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#endif
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return 0;
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}
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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init_plls();
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k2g_mux_config();
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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void spl_init_keystone_plls(void)
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{
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init_plls();
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}
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#endif
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#ifdef CONFIG_TI_SECURE_DEVICE
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void board_pmmc_image_process(ulong pmmc_image, size_t pmmc_size)
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{
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int id = env_get_ulong("dev_pmmc", 10, 0);
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int ret;
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if (!rproc_is_initialized())
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rproc_init();
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ret = rproc_load(id, pmmc_image, pmmc_size);
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printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
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id, pmmc_image, pmmc_size, ret ? " Failed!" : " Success!");
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if (!ret)
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rproc_start(id);
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}
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U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_PMMC, board_pmmc_image_process);
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#endif
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