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https://github.com/AsahiLinux/u-boot
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e6e3a3d9fc
Distinguish more clearly between source files meant for producing .dtb from those meant for producing .dtbo. No functional change, as we currently have rules for producing a foo.dtbo from either foo.dts or foo.dtso. Note that in the linux tree, all device tree overlay sources have been renamed to .dtso, and the .dts->.dtbo rule is gone since v6.5 (commit 81d362732bac). So this is also a step towards staying closer to linux with respect to both Kbuild and device tree sources. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
351 lines
7.2 KiB
Text
351 lines
7.2 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* dts file for KV260 revA Carrier Card
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*
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* (C) Copyright 2020 - 2021, Xilinx, Inc.
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*
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* SD level shifter:
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* "A" – A01 board un-modified (NXP)
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* "Y" – A01 board modified with legacy interposer (Nexperia)
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* "Z" – A01 board modified with Diode interposer
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*
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* Michal Simek <michal.simek@amd.com>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/net/ti-dp83867.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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/dts-v1/;
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/plugin/;
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&{/} {
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compatible = "xlnx,zynqmp-sk-kv260-revA",
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"xlnx,zynqmp-sk-kv260-revY",
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"xlnx,zynqmp-sk-kv260-revZ",
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"xlnx,zynqmp-sk-kv260", "xlnx,zynqmp";
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model = "ZynqMP KV260 revA";
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};
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&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
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#address-cells = <1>;
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#size-cells = <0>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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u14: ina260@40 { /* u14 */
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compatible = "ti,ina260";
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#io-channel-cells = <1>;
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label = "ina260-u14";
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reg = <0x40>;
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};
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/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
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};
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&amba {
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ina260-u14 {
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compatible = "iio-hwmon";
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io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
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};
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si5332_0: si5332_0 { /* u17 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <125000000>;
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};
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si5332_1: si5332_1 { /* u17 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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si5332_2: si5332_2 { /* u17 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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si5332_3: si5332_3 { /* u17 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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};
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si5332_4: si5332_4 { /* u17 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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si5332_5: si5332_5 { /* u17 */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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};
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/* DP/USB 3.0 and SATA */
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&psgtr {
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status = "okay";
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/* pcie, usb3, sata */
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clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
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clock-names = "ref0", "ref1", "ref2";
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};
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&sata {
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status = "okay";
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/* SATA OOB timing settings */
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ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
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ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
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ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
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ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
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ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
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ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
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ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
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phy-names = "sata-phy";
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phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
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};
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&zynqmp_dpsub {
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status = "okay";
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phy-names = "dp-phy0", "dp-phy1";
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phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
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assigned-clock-rates = <27000000>, <25000000>, <300000000>;
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};
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&zynqmp_dpdma {
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status = "okay";
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assigned-clock-rates = <600000000>;
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};
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&usb0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usb0_default>;
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phy-names = "usb3-phy";
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phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
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usbhub: usb5744 { /* u43 */
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compatible = "microchip,usb5744";
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reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
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};
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};
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&dwc3_0 {
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status = "okay";
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dr_mode = "host";
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snps,usb3_lpm_capable;
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maximum-speed = "super-speed";
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};
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&sdhci1 { /* on CC with tuned parameters */
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sdhci1_default>;
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/*
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* SD 3.0 requires level shifter and this property
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* should be removed if the board has level shifter and
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* need to work in UHS mode
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*/
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no-1-8-v;
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disable-wp;
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xlnx,mio-bank = <1>;
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assigned-clock-rates = <187498123>;
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bus-width = <8>;
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};
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&gem3 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem3_default>;
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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assigned-clock-rates = <250000000>;
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mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy0: ethernet-phy@1 {
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#phy-cells = <1>;
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reg = <1>;
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compatible = "ethernet-phy-id2000.a231";
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,dp83867-rxctrl-strap-quirk;
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reset-assert-us = <100>;
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reset-deassert-us = <280>;
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reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&pinctrl0 {
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status = "okay";
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pinctrl_uart1_default: uart1-default {
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conf {
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groups = "uart1_9_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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drive-strength = <12>;
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};
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conf-rx {
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pins = "MIO37";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO36";
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bias-disable;
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output-enable;
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};
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mux {
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groups = "uart1_9_grp";
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function = "uart1";
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};
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};
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pinctrl_i2c1_default: i2c1-default {
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conf {
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groups = "i2c1_6_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux {
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groups = "i2c1_6_grp";
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function = "i2c1";
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};
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};
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pinctrl_i2c1_gpio: i2c1-gpio {
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conf {
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groups = "gpio0_24_grp", "gpio0_25_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux {
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groups = "gpio0_24_grp", "gpio0_25_grp";
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function = "gpio0";
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};
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};
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pinctrl_gem3_default: gem3-default {
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conf {
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groups = "ethernet3_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO70", "MIO72", "MIO74";
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bias-high-impedance;
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low-power-disable;
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};
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conf-bootstrap {
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pins = "MIO71", "MIO73", "MIO75";
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bias-disable;
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output-enable;
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low-power-disable;
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};
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conf-tx {
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pins = "MIO64", "MIO65", "MIO66",
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"MIO67", "MIO68", "MIO69";
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bias-disable;
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output-enable;
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low-power-enable;
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};
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conf-mdio {
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groups = "mdio3_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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output-enable;
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};
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mux-mdio {
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function = "mdio3";
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groups = "mdio3_0_grp";
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};
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mux {
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function = "ethernet3";
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groups = "ethernet3_0_grp";
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};
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};
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pinctrl_usb0_default: usb0-default {
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conf {
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groups = "usb0_0_grp";
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO52", "MIO53", "MIO55";
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bias-high-impedance;
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drive-strength = <12>;
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slew-rate = <SLEW_RATE_FAST>;
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};
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conf-tx {
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pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
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"MIO60", "MIO61", "MIO62", "MIO63";
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bias-disable;
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output-enable;
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drive-strength = <4>;
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slew-rate = <SLEW_RATE_SLOW>;
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};
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mux {
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groups = "usb0_0_grp";
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function = "usb0";
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};
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};
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pinctrl_sdhci1_default: sdhci1-default {
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conf {
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groups = "sdio1_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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bias-disable;
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};
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conf-cd {
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groups = "sdio1_cd_0_grp";
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bias-high-impedance;
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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mux-cd {
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groups = "sdio1_cd_0_grp";
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function = "sdio1_cd";
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};
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mux {
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groups = "sdio1_0_grp";
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function = "sdio1";
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};
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};
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};
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&uart1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1_default>;
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};
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