mirror of
https://github.com/AsahiLinux/u-boot
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181d1684ca
Synchronise device tree with linux v5.19-rc5. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
278 lines
6.3 KiB
Text
278 lines
6.3 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2018 Boundary Devices
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* Copyright 2021 Lucas Stach <dev@lynxeye.de>
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*/
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#include "imx8mq.dtsi"
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/ {
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model = "Boundary Devices i.MX8MQ Nitrogen8M";
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compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq";
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chosen {
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stdout-path = &uart1;
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};
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reg_1p8v: regulator-fixed-1v8 {
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compatible = "regulator-fixed";
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regulator-name = "1P8V";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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reg_snvs: regulator-fixed-snvs {
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compatible = "regulator-fixed";
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regulator-name = "VDD_SNVS";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&{/opp-table/opp-800000000} {
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opp-microvolt = <1000000>;
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};
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&{/opp-table/opp-1000000000} {
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opp-microvolt = <1000000>;
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};
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&A53_0 {
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cpu-supply = <®_arm_dram>;
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};
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&A53_1 {
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cpu-supply = <®_arm_dram>;
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};
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&A53_2 {
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cpu-supply = <®_arm_dram>;
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};
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&A53_3 {
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cpu-supply = <®_arm_dram>;
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@4 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <4>;
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interrupt-parent = <&gpio1>;
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interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
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reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <300>;
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};
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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i2c-mux@70 {
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compatible = "nxp,pca9546";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1_pca9546>;
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reg = <0x70>;
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reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c1a: i2c@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg_arm_dram: regulator@60 {
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compatible = "fcs,fan53555";
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reg = <0x60>;
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regulator-name = "VDD_ARM_DRAM_1V";
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-always-on;
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};
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};
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i2c1b: i2c@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg_dram_1p1v: regulator@60 {
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compatible = "fcs,fan53555";
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reg = <0x60>;
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regulator-name = "NVCC_DRAM_1P1V";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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regulator-always-on;
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};
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};
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i2c1c: i2c@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg_soc_gpu_vpu: regulator@60 {
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compatible = "fcs,fan53555";
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reg = <0x60>;
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regulator-name = "VDD_SOC_GPU_VPU";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <900000>;
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regulator-always-on;
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};
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};
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i2c1d: i2c@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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&pgc_gpu {
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power-supply = <®_soc_gpu_vpu>;
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};
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&pgc_vpu {
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power-supply = <®_soc_gpu_vpu>;
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&usdhc1 {
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assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
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assigned-clock-rates = <400000000>;
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
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vqmmc-supply = <®_1p8v>;
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vmmc-supply = <®_snvs>;
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bus-width = <8>;
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non-removable;
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no-mmc-hs400;
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no-sdio;
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no-sd;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
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MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
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MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
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MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
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MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
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MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
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MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
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MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
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MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
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MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0xd1
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MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
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MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
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MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
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MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0xd1
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MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x1
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MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x41
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000022
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MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000022
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>;
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};
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pinctrl_i2c1_pca9546: i2c1-pca9546grp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
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MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
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MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
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>;
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};
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pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
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>;
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};
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pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
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fsl,pins = <
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MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
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MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
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MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
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MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
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MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
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MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
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MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
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MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
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MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
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MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
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>;
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};
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pinctrl_wdog: wdoggrp {
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fsl,pins = <
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MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
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>;
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};
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};
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