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6c747f4ad4
According to hardware implementation, a single outer shareable global coherence group is defined. Inner shareable has not bee enabled. Signed-off-by: York Sun <yorksun@freescale.com>
136 lines
3.6 KiB
C
136 lines
3.6 KiB
C
/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARMV8_MMU_H_
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#define _ASM_ARMV8_MMU_H_
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#ifdef __ASSEMBLY__
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#define _AC(X, Y) X
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#else
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#define _AC(X, Y) (X##Y)
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#endif
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#define UL(x) _AC(x, UL)
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/***************************************************************/
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/*
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* The following definitions are related each other, shoud be
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* calculated specifically.
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*/
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#define VA_BITS (42) /* 42 bits virtual address */
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/* PAGE_SHIFT determines the page size */
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#undef PAGE_SIZE
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#define PAGE_SHIFT 16
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#define PAGE_SIZE (1 << PAGE_SHIFT)
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#define PAGE_MASK (~(PAGE_SIZE-1))
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/*
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* section address mask and size definitions.
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*/
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#define SECTION_SHIFT 29
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#define SECTION_SIZE (UL(1) << SECTION_SHIFT)
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#define SECTION_MASK (~(SECTION_SIZE-1))
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/***************************************************************/
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/*
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* Memory types
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*/
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#define MT_DEVICE_NGNRNE 0
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#define MT_DEVICE_NGNRE 1
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#define MT_DEVICE_GRE 2
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#define MT_NORMAL_NC 3
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#define MT_NORMAL 4
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#define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \
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(0x04 << (MT_DEVICE_NGNRE*8)) | \
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(0x0c << (MT_DEVICE_GRE*8)) | \
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(0x44 << (MT_NORMAL_NC*8)) | \
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(UL(0xff) << (MT_NORMAL*8)))
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/*
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* Hardware page table definitions.
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*
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* Level 2 descriptor (PMD).
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*/
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#define PMD_TYPE_MASK (3 << 0)
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#define PMD_TYPE_FAULT (0 << 0)
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#define PMD_TYPE_TABLE (3 << 0)
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#define PMD_TYPE_SECT (1 << 0)
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/*
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* Section
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*/
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#define PMD_SECT_OUTER_SHARE (2 << 8)
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#define PMD_SECT_INNER_SHARE (3 << 8)
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#define PMD_SECT_AF (1 << 10)
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#define PMD_SECT_NG (1 << 11)
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#define PMD_SECT_PXN (UL(1) << 53)
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#define PMD_SECT_UXN (UL(1) << 54)
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/*
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* AttrIndx[2:0]
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*/
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#define PMD_ATTRINDX(t) ((t) << 2)
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#define PMD_ATTRINDX_MASK (7 << 2)
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/*
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* TCR flags.
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*/
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#define TCR_T0SZ(x) ((64 - (x)) << 0)
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#define TCR_IRGN_NC (0 << 8)
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#define TCR_IRGN_WBWA (1 << 8)
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#define TCR_IRGN_WT (2 << 8)
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#define TCR_IRGN_WBNWA (3 << 8)
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#define TCR_IRGN_MASK (3 << 8)
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#define TCR_ORGN_NC (0 << 10)
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#define TCR_ORGN_WBWA (1 << 10)
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#define TCR_ORGN_WT (2 << 10)
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#define TCR_ORGN_WBNWA (3 << 10)
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#define TCR_ORGN_MASK (3 << 10)
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#define TCR_SHARED_NON (0 << 12)
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#define TCR_SHARED_OUTER (1 << 12)
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#define TCR_SHARED_INNER (2 << 12)
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#define TCR_TG0_4K (0 << 14)
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#define TCR_TG0_64K (1 << 14)
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#define TCR_TG0_16K (2 << 14)
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#define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */
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#define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */
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#define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */
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/* PTWs cacheable, inner/outer WBWA and non-shareable */
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#define TCR_FLAGS (TCR_TG0_64K | \
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TCR_SHARED_NON | \
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TCR_ORGN_WBWA | \
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TCR_IRGN_WBWA | \
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TCR_T0SZ(VA_BITS))
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#ifndef __ASSEMBLY__
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void set_pgtable_section(u64 *page_table, u64 index,
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u64 section, u64 memory_type);
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static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
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{
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asm volatile("dsb sy");
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if (el == 1) {
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asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
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asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
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asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
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} else if (el == 2) {
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asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
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asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
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asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
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} else if (el == 3) {
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asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
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asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
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asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
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} else {
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hang();
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}
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asm volatile("isb");
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}
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#endif
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#endif /* _ASM_ARMV8_MMU_H_ */
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