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2fccd2d96b
This is an implementation of GPIOs for Tegra that uses driver model. It has been tested on trimslice and also using the new iotrace feature. The implementation uses a top-level GPIO device (which has no actual GPIOS). Under this all the banks are created as separate GPIO devices. The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7, ..., Z0..Z7, AA0..AA7, etc. Since driver model is not yet available before relocation, or in SPL, a special function is provided for seaboard's SPL code. Signed-off-by: Simon Glass <sjg@chromium.org> |
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ap.h | ||
apb_misc.h | ||
board.h | ||
clk_rst.h | ||
clock.h | ||
funcmux.h | ||
fuse.h | ||
gp_padctrl.h | ||
gpio.h | ||
mmc.h | ||
pinmux.h | ||
pmc.h | ||
scu.h | ||
sys_proto.h | ||
tegra.h | ||
tegra_i2c.h | ||
tegra_mmc.h | ||
timer.h | ||
uart.h | ||
usb.h | ||
warmboot.h |