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68b3baaf3b
Update the bootflow svg diagram and reuse across the platforms as they are common. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
248 lines
6.9 KiB
ReStructuredText
248 lines
6.9 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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.. sectionauthor:: Vignesh Raghavendra <vigneshr@ti.com>
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AM62 Platforms
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===============
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Introduction:
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-------------
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The AM62 SoC family is the follow on AM335x built on the K3 Multicore
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SoC architecture platform, providing ultra-low-power modes, dual
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display, multi-sensor edge compute, security and other BOM-saving
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integrations. The AM62 SoC targets a broad market to enable
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applications such as Industrial HMI, PLC/CNC/Robot control, Medical
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Equipment, Building Automation, Appliances and more.
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Some highlights of this SoC are:
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* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
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Pin-to-pin compatible options for single and quad core are available.
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* Cortex-M4F for general-purpose or safety usage.
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* Dual display support, providing 24-bit RBG parallel interface and
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OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display
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resolution.
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* Selectable GPU support, up to 8GFLOPS, providing better user experience
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in 3D graphic display case and Android.
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* PRU(Programmable Realtime Unit) support for customized programmable
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interfaces/IOs.
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* Integrated Giga-bit Ethernet switch supporting up to a total of two
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external ports (TSN capable).
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* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
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NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
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1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
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* Dedicated Centralized System Controller for Security, Power, and
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Resource Management.
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* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only,
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enabling battery powered system design.
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More details can be found in the Technical Reference Manual:
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https://www.ti.com/lit/pdf/spruiv7
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Boot Flow:
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----------
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Below is the pictorial representation of boot flow:
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.. image:: img/boot_diagram_k3_current.svg
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- Here TIFS acts as master and provides all the critical services. R5/A53
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requests TIFS to get these services done as shown in the above diagram.
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Sources:
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--------
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.. include:: k3.rst
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:start-after: .. k3_rst_include_start_boot_sources
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:end-before: .. k3_rst_include_end_boot_sources
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Build procedure:
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----------------
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1. Trusted Firmware-A:
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.. code-block:: bash
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$ make CROSS_COMPILE=aarch64-none-linux-gnu- ARCH=aarch64 PLAT=k3 \
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TARGET_BOARD=lite SPD=opteed
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2. OP-TEE:
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.. code-block:: bash
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$ make PLATFORM=k3 CFG_ARM64_core=y CROSS_COMPILE=arm-none-linux-gnueabihf- \
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CROSS_COMPILE64=aarch64-none-linux-gnu-
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3. U-Boot:
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* 3.1 R5:
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.. code-block:: bash
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$ make ARCH=arm am62x_evm_r5_defconfig
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$ make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- \
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BINMAN_INDIRS=<path/to/ti-linux-firmware>
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* 3.2 A53:
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.. code-block:: bash
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$ make ARCH=arm am62x_evm_a53_defconfig
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$ make ARCH=arm CROSS_COMPILE=aarch64-none-linux-gnu- \
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BL31=<path/to/trusted-firmware-a/dir>/build/k3/lite/release/bl31.bin \
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TEE=<path/to/optee_os/dir>/out/arm-plat-k3/core/tee-raw.bin \
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BINMAN_INDIRS=<path/to/ti-linux-firmware>
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Target Images
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--------------
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In order to boot we need tiboot3.bin, tispl.bin and u-boot.img. Each SoC
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variant (GP, HS-FS, HS-SE) requires a different source for these files.
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- GP
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* tiboot3-am62x-gp-evm.bin from step 3.1
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* tispl.bin_unsigned, u-boot.img_unsigned from step 3.2
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- HS-FS
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* tiboot3-am62x-hs-fs-evm.bin from step 3.1
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* tispl.bin, u-boot.img from step 3.2
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- HS-SE
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* tiboot3-am62x-hs-evm.bin from step 3.1
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* tispl.bin, u-boot.img from step 3.2
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Image formats:
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--------------
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- tiboot3.bin:
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.. code-block:: text
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+-----------------------+
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| X.509 |
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| Certificate |
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| +-------------------+ |
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| | | |
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| | R5 | |
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| | u-boot-spl.bin | |
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| +-------------------+ |
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| |TIFS with board cfg| |
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| +-------------------+ |
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| | FIT header | |
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| | +---------------+ | |
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| | | | | |
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| | | DTB 1...N | | |
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| | +---------------+ | |
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| +-------------------+ |
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+-----------------------+
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- tispl.bin
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.. code-block:: text
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+-----------------------+
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| FIT HEADER |
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| +-------------------+ |
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| | A53 TF-A | |
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| +-------------------+ |
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| | A53 OP-TEE | |
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| +-------------------+ |
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| | R5 DM FW | |
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| +-------------------+ |
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| | A53 SPL | |
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| +-------------------+ |
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| | SPL DTB 1...N | |
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| +-------------------+ |
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+-----------------------+
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A53 SPL DDR Memory Layout
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-------------------------
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This provides an overview memory usage in A53 SPL stage.
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.. list-table::
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:widths: 16 16 16
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:header-rows: 1
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* - Region
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- Start Address
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- End Address
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* - EMPTY
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- 0x80000000
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- 0x80080000
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* - TEXT BASE
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- 0x80080000
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- 0x800d8000
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* - EMPTY
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- 0x800d8000
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- 0x80200000
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* - BMP IMAGE
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- 0x80200000
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- 0x80b77660
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* - STACK
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- 0x80b77660
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- 0x80b77e60
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* - GD
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- 0x80b77e60
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- 0x80b78000
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* - MALLOC
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- 0x80b78000
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- 0x80b80000
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* - EMPTY
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- 0x80b80000
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- 0x80c80000
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* - BSS
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- 0x80c80000
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- 0x80d00000
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* - BLOBS
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- 0x80d00000
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- 0x80d00400
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* - EMPTY
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- 0x80d00400
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- 0x81000000
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Switch Setting for Boot Mode
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----------------------------
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Boot Mode pins provide means to select the boot mode and options before the
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device is powered up. After every POR, they are the main source to populate
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the Boot Parameter Tables.
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The following table shows some common boot modes used on AM62 platform. More
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details can be found in the Technical Reference Manual:
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https://www.ti.com/lit/pdf/spruiv7 under the `Boot Mode Pins` section.
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*Boot Modes*
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============ ============= =============
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Switch Label SW2: 12345678 SW3: 12345678
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============ ============= =============
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SD 01000000 11000010
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OSPI 00000000 11001110
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EMMC 00000000 11010010
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UART 00000000 11011100
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USB DFU 00000000 11001010
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============ ============= =============
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For SW2 and SW1, the switch state in the "ON" position = 1.
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