mirror of
https://github.com/AsahiLinux/u-boot
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837f1ba05c
PCI1 LAW mapping should use CFG_PCI1_MEM_PHY and not _BASE address. Enable LBC and ECM errors and clear error registers. Add tftpflash env var to get uboot from tftp server and flash it. Add pci/pcie convenience env vars to display register space: "run pcie3regs" to see all pcie3 ccsr registers "run pcie3cfg" to see all cfg registers Whitespace cleanup and MPC8544DS.h Enable CONFIG_INTERRUPTS. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
624 lines
19 KiB
C
624 lines
19 KiB
C
/*
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* Copyright 2007 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* mpc8544ds board configuration file
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*
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
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#define CONFIG_MPC8544 1
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#define CONFIG_MPC8544DS 1
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#define CONFIG_PCI 1 /* Enable PCI/PCIE */
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#define CONFIG_PCI1 1 /* PCI controller 1 */
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#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
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#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
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#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
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#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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#undef CONFIG_DDR_DLL
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#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
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#define CONFIG_DDR_ECC /* only for ECC DDR module */
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
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#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
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#define CONFIG_DDR_ECC_CMD
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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/*
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* When initializing flash, if we cannot find the manufacturer ID,
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* assume this is the AMD flash associated with the CDS board.
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* This allows booting from a promjet.
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*/
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#define CONFIG_ASSUME_AMD_FLASH
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#define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */
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#ifndef __ASSEMBLY__
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extern unsigned long get_board_sys_clk(unsigned long dummy);
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#endif
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
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/*
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* These can be toggled for performance analysis, otherwise use default.
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*/
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#define CONFIG_L2_CACHE /* toggle L2 cache */
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#define CONFIG_BTB /* toggle branch predition */
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#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
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#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */
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/*
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* Only possible on E500 Version 2 or newer cores.
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*/
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#define CONFIG_ENABLE_36BIT_PHYS 1
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
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#undef CFG_DRAM_TEST /* memory test, takes time */
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#define CFG_MEMTEST_START 0x00200000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00400000
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#define CFG_ALT_MEMTEST
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#define CONFIG_PANIC_HANG /* do not reset board on panic */
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/*
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*/
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#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
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#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
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#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
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#define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000)
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#define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000)
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#define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000)
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#define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000)
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/*
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* DDR Setup
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*/
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#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
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#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
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#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
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/*
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* Make sure required options are set
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*/
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#ifndef CONFIG_SPD_EEPROM
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#error ("CONFIG_SPD_EEPROM is required")
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#endif
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#undef CONFIG_CLOCKS_IN_MHZ
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/*
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* Memory map
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
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*
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* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
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*
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* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
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*
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* 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
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* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
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*
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* Localbus cacheable
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*
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* 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
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* 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
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*
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* Localbus non-cacheable
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*
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* 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
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* 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
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* 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
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*
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*/
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/*
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* Local Bus Definitions
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*/
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#define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */
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#define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
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#define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */
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#define CFG_BR0_PRELIM 0xff801001
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#define CFG_BR1_PRELIM 0xfe801001
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#define CFG_OR0_PRELIM 0xff806e65
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#define CFG_OR1_PRELIM 0xff806e65
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#define CFG_FLASH_BANKS_LIST {0xfe800000,CFG_FLASH_BASE}
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#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
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#define CFG_MAX_FLASH_SECT 128 /* sectors per device */
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#undef CFG_FLASH_CHECKSUM
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#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
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#define CFG_FLASH_CFI_DRIVER
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#define CFG_FLASH_CFI
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#define CFG_FLASH_EMPTY_INFO
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#define CFG_LBC_NONCACHE_BASE 0xf8000000
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#define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */
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#define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
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#define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */
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#define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
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#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
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#define PIXIS_ID 0x0 /* Board ID at offset 0 */
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#define PIXIS_VER 0x1 /* Board version at offset 1 */
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#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
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#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
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#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
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* register */
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#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
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#define PIXIS_VCTL 0x10 /* VELA Control Register */
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#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
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#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
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#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
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#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
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#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
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#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
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#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
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/* define to use L1 as initial stack */
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#define CONFIG_L1_INIT_RAM 1
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#define CFG_INIT_L1_LOCK 1
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#define CFG_INIT_L1_ADDR 0xf4010000 /* Initial L1 address */
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#define CFG_INIT_L1_END 0x00004000 /* End of used area in RAM */
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/* define to use L2SRAM as initial stack */
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#undef CONFIG_L2_INIT_RAM
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#define CFG_INIT_L2_ADDR 0xf8fc0000
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#define CFG_INIT_L2_END 0x00040000 /* End of used area in RAM */
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#ifdef CONFIG_L1_INIT_RAM
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#define CFG_INIT_RAM_ADDR CFG_INIT_L1_ADDR
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#define CFG_INIT_RAM_END CFG_INIT_L1_END
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#else
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#define CFG_INIT_RAM_ADDR CFG_INIT_L2_ADDR
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#define CFG_INIT_RAM_END CFG_INIT_L2_END
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#endif
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#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
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#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
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/* Serial Port - controlled on board with jumper J8
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* open - index 2
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* shorted - index 1
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*/
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#define CONFIG_CONS_INDEX 1
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#undef CONFIG_SERIAL_SOFTWARE_FIFO
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#define CFG_NS16550
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#define CFG_NS16550_SERIAL
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#define CFG_NS16550_REG_SIZE 1
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#define CFG_NS16550_CLK get_bus_freq(0)
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
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#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
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#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
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/* Use the HUSH parser */
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#define CFG_HUSH_PARSER
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#ifdef CFG_HUSH_PARSER
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#define CFG_PROMPT_HUSH_PS2 "> "
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#endif
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/* pass open firmware flat tree */
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#define CONFIG_OF_FLAT_TREE 1
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#define CONFIG_OF_BOARD_SETUP 1
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/* maximum size of the flat tree (8K) */
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#define OF_FLAT_TREE_MAX_SIZE 8192
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#define OF_CPU "PowerPC,8544@0"
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#define OF_SOC "soc8544@e0000000"
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#define OF_TBCLK (bd->bi_busfreq / 8)
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#define OF_STDOUT_PATH "/soc8544@e0000000/serial@4500"
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/* I2C */
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#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
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#define CONFIG_HARD_I2C /* I2C with hardware support */
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#undef CONFIG_SOFT_I2C /* I2C bit-banged */
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
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#define CFG_I2C_OFFSET 0x3100
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/*
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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*/
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#define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
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#define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
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#define CFG_PCI1_MEM_BASE 0xc0000000
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#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
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#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
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#define CFG_PCI1_IO_BASE 0x00000000
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#define CFG_PCI1_IO_PHYS 0xe1000000
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#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
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/* PCI view of System Memory */
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#define CFG_PCI_MEMORY_BUS 0x00000000
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#define CFG_PCI_MEMORY_PHYS 0x00000000
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#define CFG_PCI_MEMORY_SIZE 0x80000000
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/* controller 2, Slot 1, tgtid 1, Base address 9000 */
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#define CFG_PCIE2_MEM_BASE 0x80000000
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#define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE
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#define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */
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#define CFG_PCIE2_IO_BASE 0x00000000
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#define CFG_PCIE2_IO_PHYS 0xe2000000
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#define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */
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/* controller 1, Slot 2,tgtid 2, Base address a000 */
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#define CFG_PCIE1_MEM_BASE 0xa0000000
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#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE
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#define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */
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#define CFG_PCIE1_MEM_BASE2 0xa8000000
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#define CFG_PCIE1_MEM_PHYS2 CFG_PCIE1_MEM_BASE2
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#define CFG_PCIE1_MEM_SIZE2 0x04000000 /* 64M */
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#define CFG_PCIE1_IO_BASE 0x00000000 /* reuse mem LAW */
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#define CFG_PCIE1_IO_PHYS 0xaf000000
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#define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */
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/* controller 3, direct to uli, tgtid 3, Base address b000 */
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#define CFG_PCIE3_MEM_BASE 0xb0000000
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#define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE
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#define CFG_PCIE3_MEM_SIZE 0x10000000 /* 256M */
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#define CFG_PCIE3_IO_BASE 0x00000000
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#define CFG_PCIE3_IO_PHYS 0xe3000000
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#define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */
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#if defined(CONFIG_PCI)
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#define CONFIG_NET_MULTI
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#define CONFIG_PCI_PNP /* do pci plug-and-play */
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#undef CONFIG_EEPRO100
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#undef CONFIG_TULIP
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#define CONFIG_RTL8139
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#ifdef CONFIG_RTL8139
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/* This macro is used by RTL8139 but not defined in PPC architecture */
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#define KSEG1ADDR(x) (x)
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#define _IO_BASE 0x00000000
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#endif
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#ifndef CONFIG_PCI_PNP
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#define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE
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#define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE
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#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
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#endif
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_DOS_PARTITION
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#define CONFIG_SCSI_AHCI
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#ifdef CONFIG_SCSI_AHCI
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#define CONFIG_SATA_ULI5288
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#define CFG_SCSI_MAX_SCSI_ID 4
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#define CFG_SCSI_MAX_LUN 1
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#define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN)
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#define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE
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#endif /* SCSCI */
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#endif /* CONFIG_PCI */
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#if defined(CONFIG_TSEC_ENET)
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#ifndef CONFIG_NET_MULTI
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#define CONFIG_NET_MULTI 1
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#endif
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC1"
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#define CONFIG_TSEC3 1
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#define CONFIG_TSEC3_NAME "eTSEC3"
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#undef CONFIG_MPC85XX_FEC
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#define CONFIG_TSEC_TBI 1 /* enable internal TBI phy */
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#define CONFIG_SGMII_RISER
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#define TSEC1_SGMII_PHY_ADDR_OFFSET 0x1c /* sgmii phy base */
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#define TSEC1_PHY_ADDR 0
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#define TSEC3_PHY_ADDR 1
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#define TSEC1_PHYIDX 0
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#define TSEC3_PHYIDX 0
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#define CONFIG_ETHPRIME "eTSEC1"
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#endif /* CONFIG_TSEC_ENET */
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/*
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* Environment
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*/
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#define CFG_ENV_IS_IN_FLASH 1
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#if CFG_MONITOR_BASE > 0xfff80000
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#define CFG_ENV_ADDR 0xfff80000
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#else
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
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#endif
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#define CFG_ENV_SIZE 0x2000
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#define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MII
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#if defined(CONFIG_PCI)
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_BEDBUG
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_SCSI
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#define CONFIG_CMD_EXT2
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#endif
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_LONGHELP /* undef to save memory */
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#define CFG_LOAD_ADDR 0x2000000 /* default load address */
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
|
#define CFG_MAXARGS 16 /* max number of command args */
|
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
|
#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
|
|
|
|
/*
|
|
* For booting Linux, the board info and command line data
|
|
* have to be in the first 8 MB of memory, since this is
|
|
* the maximum mapped by the Linux kernel during initialization.
|
|
*/
|
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
|
|
|
|
/* Cache Configuration */
|
|
#define CFG_DCACHE_SIZE 32768
|
|
#define CFG_CACHELINE_SIZE 32
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/
|
|
#endif
|
|
|
|
/*
|
|
* Internal Definitions
|
|
*
|
|
* Boot Flags
|
|
*/
|
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
|
|
|
#if defined(CONFIG_CMD_KGDB)
|
|
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
|
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
|
|
#endif
|
|
|
|
/*
|
|
* Environment Configuration
|
|
*/
|
|
|
|
/* The mac addresses for all ethernet interface */
|
|
#if defined(CONFIG_TSEC_ENET)
|
|
#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
|
|
#define CONFIG_HAS_ETH1
|
|
#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
|
|
#define CONFIG_HAS_ETH2
|
|
#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD
|
|
#define CONFIG_HAS_ETH3
|
|
#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD
|
|
#endif
|
|
|
|
#define CONFIG_IPADDR 192.168.1.251
|
|
|
|
#define CONFIG_HOSTNAME 8544ds_unknown
|
|
#define CONFIG_ROOTPATH /nfs/mpc85xx
|
|
#define CONFIG_BOOTFILE 8544ds/uImage.uboot
|
|
#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
|
|
|
|
#define CONFIG_SERVERIP 192.168.0.1
|
|
#define CONFIG_GATEWAYIP 192.168.0.1
|
|
#define CONFIG_NETMASK 255.255.0.0
|
|
|
|
#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
|
|
|
|
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
|
|
#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
|
|
|
|
#define CONFIG_BAUDRATE 115200
|
|
|
|
#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3)
|
|
#define PCIE_ENV \
|
|
"pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
|
|
"echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
|
|
"pcieerr=md ${a}020 1; md ${a}e00 e;" \
|
|
"pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
|
|
"pci d.w $b.0 56 1;" \
|
|
"pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \
|
|
"pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;" \
|
|
"pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \
|
|
"pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \
|
|
"pci w $b.0 130 ffffffff\0" \
|
|
"pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
|
|
"pcie1regs=setenv a e000a; run pciereg\0" \
|
|
"pcie2regs=setenv a e0009; run pciereg\0" \
|
|
"pcie3regs=setenv a e000b; run pciereg\0" \
|
|
"pcie1cfg=setenv b 3; run pciecfg\0" \
|
|
"pcie2cfg=setenv b 5; run pciecfg\0" \
|
|
"pcie3cfg=setenv b 0; run pciecfg\0" \
|
|
"pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \
|
|
"pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \
|
|
"pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \
|
|
"pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \
|
|
"pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \
|
|
"pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0"
|
|
#else
|
|
#define PCIE_ENV ""
|
|
#endif
|
|
|
|
#if defined(CONFIG_PCI1)
|
|
#define PCI_ENV \
|
|
"pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
|
|
"echo e;md ${a}e00 9\0" \
|
|
"pci1regs=setenv a e0008; run pcireg\0" \
|
|
"pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
|
|
"pci d.w $b.0 56 1\0" \
|
|
"pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \
|
|
"pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \
|
|
"pci1err=setenv a e0008; setenv b 7; run pcierr\0" \
|
|
"pci1errc=setenv a e0008; setenv b 7; run pcierrc\0"
|
|
#else
|
|
#define PCI_ENV ""
|
|
#endif
|
|
|
|
#if defined(CONFIG_TSEC_ENET)
|
|
#define ENET_ENV \
|
|
"enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \
|
|
"md ${a}098 2\0" \
|
|
"enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \
|
|
"enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \
|
|
"enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \
|
|
"echo mib;md ${a}680 31\0" \
|
|
"enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \
|
|
"enet1regs=setenv a e0024; run enetreg\0" \
|
|
"enet3regs=setenv a e0026; run enetreg\0"
|
|
#else
|
|
#define ENET_ENV ""
|
|
#endif
|
|
|
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
"netdev=eth0\0" \
|
|
"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
|
|
"tftpflash=tftpboot $loadaddr $uboot; " \
|
|
"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
|
|
"erase " MK_STR(TEXT_BASE) " +$filesize; " \
|
|
"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
|
|
"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
|
|
"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
|
|
"consoledev=ttyS0\0" \
|
|
"ramdiskaddr=2000000\0" \
|
|
"ramdiskfile=8544ds/ramdisk.uboot\0" \
|
|
"dtbaddr=c00000\0" \
|
|
"dtbfile=8544ds/mpc8544ds.dtb\0" \
|
|
"bdev=sda3\0" \
|
|
"eoi=mw e00400b0 0\0" \
|
|
"iack=md e00400a0 1\0" \
|
|
"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \
|
|
"md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \
|
|
"ddrregs=setenv a e0002; run ddrreg\0" \
|
|
"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \
|
|
"md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \
|
|
"guregs=setenv a e00e0; run gureg\0" \
|
|
"ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \
|
|
"ecmregs=setenv a e0001; run ecmreg\0" \
|
|
"lawregs=md e0000c08 4b\0" \
|
|
"lbcregs=md e0005000 36\0" \
|
|
"dma0regs=md e0021100 12\0" \
|
|
"dma1regs=md e0021180 12\0" \
|
|
"dma2regs=md e0021200 12\0" \
|
|
"dma3regs=md e0021280 12\0" \
|
|
PCIE_ENV \
|
|
PCI_ENV \
|
|
ENET_ENV
|
|
|
|
|
|
#define CONFIG_NFSBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/nfs rw " \
|
|
"nfsroot=$serverip:$rootpath " \
|
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $dtbaddr $dtbfile;" \
|
|
"bootm $loadaddr - $dtbaddr"
|
|
|
|
|
|
#define CONFIG_RAMBOOTCOMMAND \
|
|
"setenv bootargs root=/dev/ram rw " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $dtbaddr $dtbfile;" \
|
|
"bootm $loadaddr $ramdiskaddr $dtbaddr"
|
|
|
|
#define CONFIG_BOOTCOMMAND \
|
|
"setenv bootargs root=/dev/$bdev rw " \
|
|
"console=$consoledev,$baudrate $othbootargs;" \
|
|
"tftp $loadaddr $bootfile;" \
|
|
"tftp $dtbaddr $dtbfile;" \
|
|
"bootm $loadaddr - $dtbaddr"
|
|
|
|
#endif /* __CONFIG_H */
|