u-boot/arch
Simon Goldschmidt 9dc61aac2d arm: socfpga: gen5: reduce SPL pre-reloc malloc
By enabling debug prints in malloc_simple, we can see that SPL for socfpga
gen5 does by far not need the 8 KiB malloc pool currently allocated for
SPL in pre-reloc phase.

On socfpga_socrates, 1304 bytes are currently used (and this increases by
~200 bytes only for the sdram/reset fixes in socfpga-next).

To prevent wasting precious SRAM space, let's reduce the initial heap used
for SPL to 2 KiB. This is still some hundred bytes more than currently
used. Also, the gen5 SPL enables stack and heap in DDR memory pretty
early. Only the initial uclass/dm parsing, serial console and DDR
initialization is done in the initial heap, so these 2 KiB should be
enough for all boards.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
2019-04-25 00:00:49 +02:00
..
arc ARC: [plat-axs10x]: migrate to DM_MMC 2019-04-18 09:12:38 +03:00
arm arm: socfpga: gen5: reduce SPL pre-reloc malloc 2019-04-25 00:00:49 +02:00
m68k m68k: ColdFire mcf5441x, add eSDHC support 2018-09-16 00:01:13 +02:00
microblaze arch: types.h: factor out fixed width typedefs to int-ll64.h 2018-09-10 20:48:16 -04:00
mips dt: bcm968380gerg: enable nand controller 2019-04-22 11:56:29 -04:00
nds32 dts: switch spi-flash to jedec, spi-nor compatible 2019-04-12 10:54:27 +05:30
nios2 .gitignore: move *.dtb and *.dtb.S patterns to the top-level .gitignore 2018-06-18 14:43:12 -04:00
powerpc powerpc: fix arch/powerpc/dts/Makefile 2019-03-22 12:15:10 -04:00
riscv dts: switch spi-flash to jedec, spi-nor compatible 2019-04-12 10:54:27 +05:30
sandbox Merge branch 'master' of git://git.denx.de/u-boot-spi 2019-04-14 00:03:06 -04:00
sh sh: bitops: add hweight*() macros 2019-02-07 15:33:21 +05:30
x86 x86: dts: switch spi-flash to jedec, spi-nor compatible 2019-04-12 10:54:27 +05:30
xtensa xtensa: use asm-generic/atomic.h 2018-09-25 21:49:18 -04:00
.gitignore
Kconfig riscv: Enable create symlink using kconfig 2019-02-27 09:12:33 +08:00