Anup Patel d2db2a8fa4 riscv: Add kconfig option to run U-Boot in S-mode ... This patch adds kconfig option RISCV_SMODE to run U-Boot in S-mode. When this opition is enabled we use s<xyz> CSRs instead of m<xyz> CSRs. It is important to note that there is no equivalent S-mode CSR for misa and mhartid CSRs so we expect M-mode runtime firmware (BBL or equivalent) to emulate misa and mhartid CSR read. In-future, we will have more patches to avoid accessing misa and mhartid CSRs from S-mode. Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>		2018-12-05 14:13:53 +08:00
..
boot.c	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
bootm.c	riscv: align bootm implementation with that of other architectures	2018-11-26 13:57:32 +08:00
cache.c	riscv: cache: Implement i/dcache [status, enable, disable]	2018-11-26 13:58:01 +08:00
crt0_riscv_efi.S	riscv: efi: Generate Microsoft PE format compliant images	2018-12-02 21:59:36 +01:00
elf_riscv32_efi.lds	SPDX: Convert single license tags to Linux Kernel style	2018-05-29 14:44:21 +08:00
elf_riscv64_efi.lds	SPDX: Convert single license tags to Linux Kernel style	2018-05-29 14:44:21 +08:00
interrupts.c	riscv: Add kconfig option to run U-Boot in S-mode	2018-12-05 14:13:53 +08:00
Makefile	riscv: Move do_reset() to a common place	2018-10-03 17:48:43 +08:00
reloc_riscv_efi.c	riscv: Remove unused _relocate arguments	2018-07-19 16:31:37 -04:00
reset.c	riscv: cosmetic: Reword do_reset() printf message.	2018-10-03 17:49:27 +08:00
setjmp.S	riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I	2018-11-26 13:57:29 +08:00