mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-25 04:23:46 +00:00
ba932bc846
Add board code and DTs for Renesas RZ/A1 SoC-based GR-Peach, which is a cheap development platform with RZ/A1H SoC. The DTs are imported from Linux 5.0.11, commit d5a2675b207d . Currently supported are UART, ethernet and RPC SPI. The board can be booted from RPC SPI by writing the u-boot.bin binary to the beginning of the SPI NOR, e.g. using the "sf" command. The board can also be booted via JTAG by setting text base to 0x20020000, loading u-boot.bin there via JTAG and executing it from that address. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
52 lines
909 B
C
52 lines
909 B
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2017 Renesas Electronics
|
|
* Copyright (C) Chris Brandt
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
|
|
#define RZA1_WDT_BASE 0xfcfe0000
|
|
#define WTCSR 0x00
|
|
#define WTCNT 0x02
|
|
#define WRCSR 0x04
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
int board_init(void)
|
|
{
|
|
gd->bd->bi_boot_params = (CONFIG_SYS_SDRAM_BASE + 0x100);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dram_init(void)
|
|
{
|
|
if (fdtdec_setup_mem_size_base() != 0)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dram_init_banksize(void)
|
|
{
|
|
fdtdec_setup_memory_banksize();
|
|
|
|
return 0;
|
|
}
|
|
|
|
void reset_cpu(ulong addr)
|
|
{
|
|
/* Dummy read (must read WRCSR:WOVF at least once before clearing) */
|
|
readb(RZA1_WDT_BASE + WRCSR);
|
|
|
|
writew(0xa500, RZA1_WDT_BASE + WRCSR);
|
|
writew(0x5a5f, RZA1_WDT_BASE + WRCSR);
|
|
writew(0x5a00, RZA1_WDT_BASE + WTCNT);
|
|
writew(0xa578, RZA1_WDT_BASE + WTCSR);
|
|
|
|
for (;;)
|
|
asm volatile("wfi");
|
|
}
|