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https://github.com/AsahiLinux/u-boot
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32413125b3
Moves below DDR specific defines to Kconfig: CONFIG_FSL_DDR_BIST CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE CONFIG_FSL_DDR_INTERACTIVE CONFIG_FSL_DDR_SYNC_REFRESH Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
70 lines
1.5 KiB
Text
70 lines
1.5 KiB
Text
menu "mpc86xx CPU"
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depends on MPC86xx
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config SYS_CPU
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default "mpc86xx"
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choice
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prompt "Target select"
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optional
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config TARGET_SBC8641D
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bool "Support sbc8641d"
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select ARCH_MPC8641
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select BOARD_EARLY_INIT_F
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config TARGET_MPC8610HPCD
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bool "Support MPC8610HPCD"
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select ARCH_MPC8610
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select BOARD_EARLY_INIT_F
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config TARGET_MPC8641HPCN
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bool "Support MPC8641HPCN"
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select ARCH_MPC8641
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select FSL_DDR_INTERACTIVE
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imply SCSI
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config TARGET_XPEDITE517X
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bool "Support xpedite517x"
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select ARCH_MPC8641
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endchoice
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config ARCH_MPC8610
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR1
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select SYS_FSL_HAS_DDR2
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config ARCH_MPC8641
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bool
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select FSL_LAW
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select SYS_FSL_HAS_DDR1
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select SYS_FSL_HAS_DDR2
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config FSL_LAW
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bool
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help
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Use Freescale common code for Local Access Window
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config SYS_CCSRBAR_DEFAULT
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hex "Default CCSRBAR address"
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default 0xff700000 if ARCH_MPC8610 || ARCH_MPC8641
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help
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Default value of CCSRBAR comes from power-on-reset. It
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is fixed on each SoC. Some SoCs can have different value
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if changed by pre-boot regime. The value here must match
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the current value in SoC. If not sure, do not change.
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config SYS_FSL_NUM_LAWS
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int "Number of local access windows"
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default 10 if ARCH_MPC8610 || ARCH_MPC8641
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help
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Number of local access windows. This is fixed per SoC.
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If not sure, do not change.
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source "board/freescale/mpc8610hpcd/Kconfig"
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source "board/freescale/mpc8641hpcn/Kconfig"
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source "board/sbc8641d/Kconfig"
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source "board/xes/xpedite517x/Kconfig"
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endmenu
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