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2c2cc3e9c0
The pinctrl and GPIO drivers are currently heavily incompatible with upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at it's own address. Introduce support for these by allowing the soc driver to specify per-pin register offsets similarly to the Linux driver. Adjust the GPIO driver to handle these too, and finally enable support for all pins with the same numbering as used in Linux. Reviewed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
35 lines
710 B
C
35 lines
710 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Qualcomm Pin control
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*
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* (C) Copyright 2018 Ramon Fried <ramon.fried@gmail.com>
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*
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*/
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#ifndef _PINCTRL_QCOM_H
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#define _PINCTRL_QCOM_H
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#include <asm/types.h>
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#include <mach/gpio.h>
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struct udevice;
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struct msm_pinctrl_data {
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struct msm_pin_data pin_data;
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int functions_count;
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const char *(*get_function_name)(struct udevice *dev,
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unsigned int selector);
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unsigned int (*get_function_mux)(unsigned int selector);
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const char *(*get_pin_name)(struct udevice *dev,
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unsigned int selector);
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};
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struct pinctrl_function {
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const char *name;
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int val;
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};
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extern struct pinctrl_ops msm_pinctrl_ops;
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int msm_pinctrl_bind(struct udevice *dev);
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#endif
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