mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-26 06:30:39 +00:00
ff159286a7
This driver manages the SPI controller present on this SoC. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Simon Glass <sjg@chromium.org>
144 lines
2.7 KiB
Text
144 lines
2.7 KiB
Text
/*
|
|
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <dt-bindings/clock/bcm6348-clock.h>
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
#include <dt-bindings/reset/bcm6348-reset.h>
|
|
#include "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "brcm,bcm6348";
|
|
|
|
aliases {
|
|
spi0 = &spi;
|
|
};
|
|
|
|
cpus {
|
|
reg = <0xfffe0000 0x4>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
cpu@0 {
|
|
compatible = "brcm,bcm6348-cpu", "mips,mips4Kc";
|
|
device_type = "cpu";
|
|
reg = <0>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
periph_osc: periph-osc {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <50000000>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
periph_clk: periph-clk {
|
|
compatible = "brcm,bcm6345-clk";
|
|
reg = <0xfffe0004 0x4>;
|
|
#clock-cells = <1>;
|
|
};
|
|
};
|
|
|
|
pflash: nor@1fc00000 {
|
|
compatible = "cfi-flash";
|
|
reg = <0x1fc00000 0x2000000>;
|
|
bank-width = <2>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ubus {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
pll_cntl: syscon@fffe0008 {
|
|
compatible = "syscon";
|
|
reg = <0xfffe0008 0x4>;
|
|
};
|
|
|
|
syscon-reboot {
|
|
compatible = "syscon-reboot";
|
|
regmap = <&pll_cntl>;
|
|
offset = <0x0>;
|
|
mask = <0x1>;
|
|
};
|
|
|
|
periph_rst: reset-controller@fffe0028 {
|
|
compatible = "brcm,bcm6345-reset";
|
|
reg = <0xfffe0028 0x4>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
wdt: watchdog@fffe021c {
|
|
compatible = "brcm,bcm6345-wdt";
|
|
reg = <0xfffe021c 0xc>;
|
|
clocks = <&periph_osc>;
|
|
};
|
|
|
|
wdt-reboot {
|
|
compatible = "wdt-reboot";
|
|
wdt = <&wdt>;
|
|
};
|
|
|
|
uart0: serial@fffe0300 {
|
|
compatible = "brcm,bcm6345-uart";
|
|
reg = <0xfffe0300 0x18>;
|
|
clocks = <&periph_osc>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio1: gpio-controller@fffe0400 {
|
|
compatible = "brcm,bcm6345-gpio";
|
|
reg = <0xfffe0400 0x4>, <0xfffe0408 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
ngpios = <5>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio0: gpio-controller@fffe0404 {
|
|
compatible = "brcm,bcm6345-gpio";
|
|
reg = <0xfffe0404 0x4>, <0xfffe040c 0x4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
spi: spi@fffe0c00 {
|
|
compatible = "brcm,bcm6348-spi";
|
|
reg = <0xfffe0c00 0xc0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&periph_clk BCM6348_CLK_SPI>;
|
|
resets = <&periph_rst BCM6348_RST_SPI>;
|
|
spi-max-frequency = <20000000>;
|
|
num-cs = <4>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
memory-controller@fffe2300 {
|
|
compatible = "brcm,bcm6338-mc";
|
|
reg = <0xfffe2300 0x38>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
};
|