mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 17:07:38 +00:00
e37650846f
Use of CONFIG_SPL_FIT_SIGNATURE=y cause CONFIG_LEGACY_IMAGE_FORMAT=n as default, this prevent boot scripts in legacy image format from working and was an unintended change in the listed fixes commits: Wrong image format for "source" command Add CONFIG_LEGACY_IMAGE_FORMAT=y to defconfig for affected boards to restore support for boot scripts in legacy image format. Fixes:3bf8e40807("board: rockchip: add Radxa ROCK5B Rk3588 board") Fixes:cf777572ca("rockchip: rockpro64: Use SDMA to boost eMMC performance") Fixes:6e2b8344d6("rockchip: rock-pi-4: Use SDMA to boost eMMC performance") Fixes:1bf49d5a4a("rockchip: rk3566-radxa-cm3-io: Update defconfig") Fixes:703c170b40("rockchip: rk3568-evb: Update defconfig") Fixes:68000f750a("rockchip: rk3568-rock-3a: Update defconfig") Fixes:6fb02589a6("rockchip: rk3588-evb: Update defconfig") Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
94 lines
2.5 KiB
Text
94 lines
2.5 KiB
Text
CONFIG_ARM=y
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CONFIG_SKIP_LOWLEVEL_INIT=y
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CONFIG_COUNTER_FREQUENCY=24000000
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CONFIG_ARCH_ROCKCHIP=y
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CONFIG_TEXT_BASE=0x00a00000
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
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CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc00000
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CONFIG_SF_DEFAULT_SPEED=24000000
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CONFIG_SF_DEFAULT_MODE=0x2000
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CONFIG_DEFAULT_DEVICE_TREE="rk3568-rock-3a"
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CONFIG_ROCKCHIP_RK3568=y
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CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
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CONFIG_ROCKCHIP_SPI_IMAGE=y
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CONFIG_SPL_SERIAL=y
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CONFIG_SPL_STACK_R_ADDR=0x600000
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CONFIG_SPL_STACK=0x400000
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CONFIG_DEBUG_UART_BASE=0xFE660000
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CONFIG_DEBUG_UART_CLOCK=24000000
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI=y
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CONFIG_SYS_LOAD_ADDR=0xc00800
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CONFIG_DEBUG_UART=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_SPL_FIT_SIGNATURE=y
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CONFIG_SPL_LOAD_FIT=y
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CONFIG_LEGACY_IMAGE_FORMAT=y
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CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-rock-3a.dtb"
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# CONFIG_DISPLAY_CPUINFO is not set
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CONFIG_DISPLAY_BOARDINFO_LATE=y
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CONFIG_SPL_MAX_SIZE=0x40000
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CONFIG_SPL_PAD_TO=0x7f8000
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CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
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CONFIG_SPL_BSS_START_ADDR=0x4000000
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CONFIG_SPL_BSS_MAX_SIZE=0x4000
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# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
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# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_SPI_LOAD=y
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CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
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CONFIG_SPL_ATF=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_PMIC=y
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CONFIG_CMD_REGULATOR=y
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# CONFIG_SPL_DOS_PARTITION is not set
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_OF_LIVE=y
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CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
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CONFIG_SPL_REGMAP=y
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CONFIG_SPL_SYSCON=y
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CONFIG_SPL_CLK=y
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CONFIG_ROCKCHIP_GPIO=y
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CONFIG_SYS_I2C_ROCKCHIP=y
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CONFIG_MISC=y
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CONFIG_SUPPORT_EMMC_RPMB=y
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CONFIG_MMC_DW=y
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CONFIG_MMC_DW_ROCKCHIP=y
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CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_SDMA=y
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CONFIG_MMC_SDHCI_ROCKCHIP=y
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CONFIG_SPI_FLASH_MACRONIX=y
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CONFIG_SPI_FLASH_XTX=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_GMAC_ROCKCHIP=y
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CONFIG_PHY_ROCKCHIP_INNO_USB2=y
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CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
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CONFIG_SPL_PINCTRL=y
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CONFIG_DM_PMIC=y
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CONFIG_PMIC_RK8XX=y
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CONFIG_REGULATOR_RK8XX=y
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CONFIG_PWM_ROCKCHIP=y
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CONFIG_SPL_RAM=y
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CONFIG_BAUDRATE=1500000
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CONFIG_DEBUG_UART_SHIFT=2
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CONFIG_SYS_NS16550_MEM32=y
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CONFIG_ROCKCHIP_SFC=y
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CONFIG_SYSRESET=y
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CONFIG_USB=y
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CONFIG_USB_XHCI_HCD=y
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CONFIG_USB_XHCI_DWC3=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_GENERIC=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_OHCI_GENERIC=y
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CONFIG_USB_DWC3=y
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CONFIG_ERRNO_STR=y
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