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c916d7c914
The Frame Manager (FMan) on QorIQ SoCs with DPAA (datapath acceleration architecture) is the ethernet contoller block. Normally it is utilized via Queue Manager (Qman) and Buffer Manager (Bman). However for boot usage the FMan supports a mode similar to QE or CPM ethernet collers called Independent mode. Additionally the FMan block supports multiple 1g and 10g interfaces as a single entity in the system rather than each controller being managed uniquely. This means we have to initialize all of Fman regardless of the number of interfaces we utilize. Different SoCs support different combinations of the number of FMan as well as the number of 1g & 10g interfaces support per Fman. We add support for the following SoCs: * P1023 - 1 Fman, 2x1g * P4080 - 2 Fman, each Fman has 4x1g and 1x10g * P204x/P3041/P5020 - 1 Fman, 5x1g, 1x10g Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Dai Haruki <dai.haruki@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Lei Xu <B33228@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
139 lines
3.6 KiB
C
139 lines
3.6 KiB
C
/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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* Andy Fleming <afleming@freescale.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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* Some part is taken from tsec.c
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*/
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#include <common.h>
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#include <miiphy.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <asm/fsl_tgec.h>
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#include <fm_eth.h>
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/*
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* Write value to the PHY for this device to the register at regnum, waiting
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* until the write is done before it returns. All PHY configuration has to be
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* done through the TSEC1 MIIM regs
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*/
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int tgec_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
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int regnum, u16 value)
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{
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u32 mdio_ctl;
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u32 stat_val;
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struct tgec_mdio_controller *regs = bus->priv;
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if (dev_addr == MDIO_DEVAD_NONE)
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return 0;
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/* Wait till the bus is free */
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stat_val = MDIO_STAT_CLKDIV(100);
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out_be32(®s->mdio_stat, stat_val);
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Set the port and dev addr */
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mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
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out_be32(®s->mdio_ctl, mdio_ctl);
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/* Set the register address */
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out_be32(®s->mdio_addr, regnum & 0xffff);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Write the value to the register */
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out_be32(®s->mdio_data, MDIO_DATA(value));
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/* Wait till the MDIO write is complete */
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while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
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;
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return 0;
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}
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/*
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* Reads from register regnum in the PHY for device dev, returning the value.
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* Clears miimcom first. All PHY configuration has to be done through the
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* TSEC1 MIIM regs
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*/
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int tgec_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
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int regnum)
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{
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u32 mdio_ctl;
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u32 stat_val;
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struct tgec_mdio_controller *regs = bus->priv;
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if (dev_addr == MDIO_DEVAD_NONE)
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return 0xffff;
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stat_val = MDIO_STAT_CLKDIV(100);
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out_be32(®s->mdio_stat, stat_val);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Set the Port and Device Addrs */
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mdio_ctl = MDIO_CTL_PORT_ADDR(port_addr) | MDIO_CTL_DEV_ADDR(dev_addr);
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out_be32(®s->mdio_ctl, mdio_ctl);
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/* Set the register address */
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out_be32(®s->mdio_addr, regnum & 0xffff);
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/* Wait till the bus is free */
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while ((in_be32(®s->mdio_stat)) & MDIO_STAT_BSY)
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;
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/* Initiate the read */
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mdio_ctl |= MDIO_CTL_READ;
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out_be32(®s->mdio_ctl, mdio_ctl);
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/* Wait till the MDIO write is complete */
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while ((in_be32(®s->mdio_data)) & MDIO_DATA_BSY)
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;
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/* Return all Fs if nothing was there */
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if (in_be32(®s->mdio_stat) & MDIO_STAT_RD_ER)
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return 0xffff;
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return in_be32(®s->mdio_data) & 0xffff;
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}
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int tgec_mdio_reset(struct mii_dev *bus)
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{
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return 0;
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}
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int fm_tgec_mdio_init(bd_t *bis, struct tgec_mdio_info *info)
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{
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struct mii_dev *bus = mdio_alloc();
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if (!bus) {
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printf("Failed to allocate FM TGEC MDIO bus\n");
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return -1;
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}
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bus->read = tgec_mdio_read;
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bus->write = tgec_mdio_write;
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bus->reset = tgec_mdio_reset;
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sprintf(bus->name, info->name);
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bus->priv = info->regs;
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return mdio_register(bus);
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}
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